1 From 4ce5a0bd3958ed248f0325bfcb95339f7c74feb2 Mon Sep 17 00:00:00 2001
2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
3 Date: Wed, 18 May 2022 15:54:57 +0100
4 Subject: [PATCH 06/12] net: mtk_eth_soc: stop passing phylink state to sgmii
7 Now that mtk_sgmii_setup_mode_force() only uses the interface mode
8 from the phylink state, pass just the interface mode into this
11 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
14 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
15 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
16 drivers/net/ethernet/mediatek/mtk_sgmii.c | 4 ++--
17 3 files changed, 4 insertions(+), 4 deletions(-)
19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
21 @@ -437,7 +437,7 @@ static void mtk_mac_config(struct phylin
22 /* Setup SGMIISYS with the determined property */
23 if (state->interface != PHY_INTERFACE_MODE_SGMII)
24 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
27 else if (phylink_autoneg_inband(mode))
28 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
30 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
31 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
32 @@ -1102,7 +1102,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
34 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
35 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
36 - const struct phylink_link_state *state);
37 + phy_interface_t interface);
38 void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex);
39 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id);
41 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
42 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
43 @@ -65,7 +65,7 @@ int mtk_sgmii_setup_mode_an(struct mtk_s
46 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
47 - const struct phylink_link_state *state)
48 + phy_interface_t interface)
52 @@ -74,7 +74,7 @@ int mtk_sgmii_setup_mode_force(struct mt
54 regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
55 val &= ~RG_PHY_SPEED_MASK;
56 - if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
57 + if (interface == PHY_INTERFACE_MODE_2500BASEX)
58 val |= RG_PHY_SPEED_3_125G;
59 regmap_write(ss->regmap[id], ss->ana_rgc3, val);