git.openwrt.org Git - openwrt/staging/mkresin.git/blob

   1 From 3261cabf5607c9f434faa4930ab5c2b0150579c4 Mon Sep 17 00:00:00 2001
   2 From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
   3 Date: Wed, 29 Nov 2017 06:23:14 +0530
   4 Subject: [PATCH] arm64: dts: ls1012a: Add LS1012A-2G5RDB board support
   5
   6 LS1012A-2G5RDB is a different design from LS1012ARDB,
   7 but has some common SoC features. Key feature on this
   8 board is 2.5Gbps SGMII.
   9
  10 Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
  11 Signed-off-by: Li Yang <leoyang.li@nxp.com>
  12 ---
  13  arch/arm64/boot/dts/freescale/Makefile             |  1 +
  14  .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts      | 86 ++++++++++++++++++++++
  15  2 files changed, 87 insertions(+)
  16  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
  17
  18 --- a/arch/arm64/boot/dts/freescale/Makefile
  19 +++ b/arch/arm64/boot/dts/freescale/Makefile
  20 @@ -1,4 +1,5 @@
  21  # SPDX-License-Identifier: GPL-2.0
  22 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
  23  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
  24  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
  25  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
  26 --- /dev/null
  27 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
  28 @@ -0,0 +1,86 @@
  29 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  30 +/*
  31 + * Device Tree file for NXP LS1012A 2G5RDB Board.
  32 + *
  33 + * Copyright 2017 NXP
  34 + *
  35 + * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
  36 + */
  37 +/dts-v1/;
  38 +
  39 +#include "fsl-ls1012a.dtsi"
  40 +
  41 +/ {
  42 +       model = "LS1012A 2G5RDB Board";
  43 +       compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
  44 +
  45 +       aliases {
  46 +               ethernet0 = &pfe_mac0;
  47 +               ethernet1 = &pfe_mac1;
  48 +       };
  49 +};
  50 +
  51 +&duart0 {
  52 +       status = "okay";
  53 +};
  54 +
  55 +&i2c0 {
  56 +       status = "okay";
  57 +};
  58 +
  59 +&qspi {
  60 +       num-cs = <2>;
  61 +       bus-num = <0>;
  62 +       status = "okay";
  63 +
  64 +       qflash0: s25fs512s@0 {
  65 +               compatible = "spansion,m25p80";
  66 +               #address-cells = <1>;
  67 +               #size-cells = <1>;
  68 +               spi-max-frequency = <20000000>;
  69 +               m25p,fast-read;
  70 +               reg = <0>;
  71 +       };
  72 +};
  73 +
  74 +&sata {
  75 +       status = "okay";
  76 +};
  77 +
  78 +&pfe {
  79 +       status = "okay";
  80 +       #address-cells = <1>;
  81 +       #size-cells = <0>;
  82 +
  83 +       ethernet@0 {
  84 +               compatible = "fsl,pfe-gemac-port";
  85 +               #address-cells = <1>;
  86 +               #size-cells = <0>;
  87 +               reg = <0x0>;    /* GEM_ID */
  88 +               fsl,gemac-bus-id = <0x0>;       /* BUS_ID */
  89 +               fsl,gemac-phy-id = <0x1>;       /* PHY_ID */
  90 +               fsl,mdio-mux-val = <0x0>;
  91 +               phy-mode = "sgmii-2500";
  92 +               fsl,pfe-phy-if-flags = <0x0>;
  93 +
  94 +               mdio@0 {
  95 +                       reg = <0x1>; /* enabled/disabled */
  96 +               };
  97 +       };
  98 +
  99 +       ethernet@1 {
 100 +               compatible = "fsl,pfe-gemac-port";
 101 +               #address-cells = <1>;
 102 +               #size-cells = <0>;
 103 +               reg = <0x1>;    /* GEM_ID */
 104 +               fsl,gemac-bus-id = < 0x0>;      /* BUS_ID */
 105 +               fsl,gemac-phy-id = < 0x2>;      /* PHY_ID */
 106 +               fsl,mdio-mux-val = <0x0>;
 107 +               phy-mode = "sgmii-2500";
 108 +               fsl,pfe-phy-if-flags = <0x0>;
 109 +
 110 +               mdio@0 {
 111 +                       reg = <0x0>; /* enabled/disabled */
 112 +               };
 113 +       };
 114 +};