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1 From c339b677f34884fdbe0e6bcdda6d59b7ae30d118 Mon Sep 17 00:00:00 2001
2 From: Naushir Patuck <naush@raspberrypi.com>
3 Date: Mon, 4 May 2020 12:25:41 +0300
4 Subject: [PATCH] media: bcm2835-unicam: Driver for CCP2/CSI2 camera
5 interface
6
7 Add a driver for the Unicam camera receiver block on BCM283x processors.
8 Compared to the bcm2835-camera driver present in staging, this driver
9 handles the Unicam block only (CSI-2 receiver), and doesn't depend on
10 the VC4 firmware running on the VPU.
11
12 The commit is made up of a series of changes cherry-picked from the
13 rpi-5.4.y branch of https://github.com/raspberrypi/linux/ with
14 additional enhancements, forward-ported to the mainline kernel.
15
16 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
17 Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
18 Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 Reported-by: kbuild test robot <lkp@intel.com>
20 ---
21 MAINTAINERS | 2 +-
22 drivers/media/platform/bcm2835/Kconfig | 15 +
23 drivers/media/platform/bcm2835/Makefile | 3 +
24 .../media/platform/bcm2835/bcm2835-unicam.c | 2825 +++++++++++++++++
25 .../media/platform/bcm2835/vc4-regs-unicam.h | 253 ++
26 5 files changed, 3097 insertions(+), 1 deletion(-)
27 create mode 100644 drivers/media/platform/bcm2835/Kconfig
28 create mode 100644 drivers/media/platform/bcm2835/Makefile
29 create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
30 create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
31
32 --- a/MAINTAINERS
33 +++ b/MAINTAINERS
34 @@ -3210,7 +3210,7 @@ M: Raspberry Pi Kernel Maintenance <kern
35 L: linux-media@vger.kernel.org
36 S: Maintained
37 F: drivers/media/platform/bcm2835/
38 -F: Documentation/devicetree/bindings/media/bcm2835-unicam.txt
39 +F: Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
40
41 BROADCOM BCM2835 ISP DRIVER
42 M: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
43 --- /dev/null
44 +++ b/drivers/media/platform/bcm2835/Kconfig
45 @@ -0,0 +1,15 @@
46 +# Broadcom VideoCore4 V4L2 camera support
47 +
48 +config VIDEO_BCM2835_UNICAM
49 + tristate "Broadcom BCM2835 Unicam video capture driver"
50 + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER
51 + depends on ARCH_BCM2835 || COMPILE_TEST
52 + select VIDEOBUF2_DMA_CONTIG
53 + select V4L2_FWNODE
54 + help
55 + Say Y here to enable support for the BCM2835 CSI-2 receiver. This is a
56 + V4L2 driver that controls the CSI-2 receiver directly, independently
57 + from the VC4 firmware.
58 +
59 + To compile this driver as a module, choose M here. The module will be
60 + called bcm2835-unicam.
61 --- /dev/null
62 +++ b/drivers/media/platform/bcm2835/Makefile
63 @@ -0,0 +1,3 @@
64 +# Makefile for BCM2835 Unicam driver
65 +
66 +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
67 --- /dev/null
68 +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
69 @@ -0,0 +1,2825 @@
70 +// SPDX-License-Identifier: GPL-2.0-only
71 +/*
72 + * BCM2835 Unicam Capture Driver
73 + *
74 + * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.
75 + *
76 + * Dave Stevenson <dave.stevenson@raspberrypi.com>
77 + *
78 + * Based on TI am437x driver by
79 + * Benoit Parrot <bparrot@ti.com>
80 + * Lad, Prabhakar <prabhakar.csengg@gmail.com>
81 + *
82 + * and TI CAL camera interface driver by
83 + * Benoit Parrot <bparrot@ti.com>
84 + *
85 + *
86 + * There are two camera drivers in the kernel for BCM283x - this one
87 + * and bcm2835-camera (currently in staging).
88 + *
89 + * This driver directly controls the Unicam peripheral - there is no
90 + * involvement with the VideoCore firmware. Unicam receives CSI-2 or
91 + * CCP2 data and writes it into SDRAM.
92 + * The only potential processing options are to repack Bayer data into an
93 + * alternate format, and applying windowing.
94 + * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P
95 + * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
96 + * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both
97 + * formats where the relevant formats are defined, and will automatically
98 + * configure the repacking as required.
99 + * Support for windowing may be added later.
100 + *
101 + * It should be possible to connect this driver to any sensor with a
102 + * suitable output interface and V4L2 subdevice driver.
103 + *
104 + * bcm2835-camera uses the VideoCore firmware to control the sensor,
105 + * Unicam, ISP, and all tuner control loops. Fully processed frames are
106 + * delivered to the driver by the firmware. It only has sensor drivers
107 + * for Omnivision OV5647, and Sony IMX219 sensors.
108 + *
109 + * The two drivers are mutually exclusive for the same Unicam instance.
110 + * The VideoCore firmware checks the device tree configuration during boot.
111 + * If it finds device tree nodes called csi0 or csi1 it will block the
112 + * firmware from accessing the peripheral, and bcm2835-camera will
113 + * not be able to stream data.
114 + */
115 +
116 +#include <linux/clk.h>
117 +#include <linux/delay.h>
118 +#include <linux/device.h>
119 +#include <linux/dma-mapping.h>
120 +#include <linux/err.h>
121 +#include <linux/init.h>
122 +#include <linux/interrupt.h>
123 +#include <linux/io.h>
124 +#include <linux/module.h>
125 +#include <linux/of_device.h>
126 +#include <linux/of_graph.h>
127 +#include <linux/pinctrl/consumer.h>
128 +#include <linux/platform_device.h>
129 +#include <linux/pm_runtime.h>
130 +#include <linux/slab.h>
131 +#include <linux/uaccess.h>
132 +#include <linux/videodev2.h>
133 +
134 +#include <media/v4l2-common.h>
135 +#include <media/v4l2-ctrls.h>
136 +#include <media/v4l2-dev.h>
137 +#include <media/v4l2-device.h>
138 +#include <media/v4l2-dv-timings.h>
139 +#include <media/v4l2-event.h>
140 +#include <media/v4l2-ioctl.h>
141 +#include <media/v4l2-fwnode.h>
142 +#include <media/videobuf2-dma-contig.h>
143 +
144 +#include "vc4-regs-unicam.h"
145 +
146 +#define UNICAM_MODULE_NAME "unicam"
147 +#define UNICAM_VERSION "0.1.0"
148 +
149 +static int debug;
150 +module_param(debug, int, 0644);
151 +MODULE_PARM_DESC(debug, "Debug level 0-3");
152 +
153 +#define unicam_dbg(level, dev, fmt, arg...) \
154 + v4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)
155 +#define unicam_info(dev, fmt, arg...) \
156 + v4l2_info(&(dev)->v4l2_dev, fmt, ##arg)
157 +#define unicam_err(dev, fmt, arg...) \
158 + v4l2_err(&(dev)->v4l2_dev, fmt, ##arg)
159 +
160 +/*
161 + * To protect against a dodgy sensor driver never returning an error from
162 + * enum_mbus_code, set a maximum index value to be used.
163 + */
164 +#define MAX_ENUM_MBUS_CODE 128
165 +
166 +/*
167 + * Stride is a 16 bit register, but also has to be a multiple of 32.
168 + */
169 +#define BPL_ALIGNMENT 32
170 +#define MAX_BYTESPERLINE ((1 << 16) - BPL_ALIGNMENT)
171 +/*
172 + * Max width is therefore determined by the max stride divided by
173 + * the number of bits per pixel. Take 32bpp as a
174 + * worst case.
175 + * No imposed limit on the height, so adopt a square image for want
176 + * of anything better.
177 + */
178 +#define MAX_WIDTH (MAX_BYTESPERLINE / 4)
179 +#define MAX_HEIGHT MAX_WIDTH
180 +/* Define a nominal minimum image size */
181 +#define MIN_WIDTH 16
182 +#define MIN_HEIGHT 16
183 +/* Default size of the embedded buffer */
184 +#define UNICAM_EMBEDDED_SIZE 8192
185 +
186 +/*
187 + * Size of the dummy buffer. Can be any size really, but the DMA
188 + * allocation works in units of page sizes.
189 + */
190 +#define DUMMY_BUF_SIZE (PAGE_SIZE)
191 +
192 +enum pad_types {
193 + IMAGE_PAD,
194 + METADATA_PAD,
195 + MAX_NODES
196 +};
197 +
198 +/*
199 + * struct unicam_fmt - Unicam media bus format information
200 + * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.
201 + * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded
202 + * out to 16bpp. 0 if n/a.
203 + * @code: V4L2 media bus format code.
204 + * @depth: Bits per pixel as delivered from the source.
205 + * @csi_dt: CSI data type.
206 + * @check_variants: Flag to denote that there are multiple mediabus formats
207 + * still in the list that could match this V4L2 format.
208 + */
209 +struct unicam_fmt {
210 + u32 fourcc;
211 + u32 repacked_fourcc;
212 + u32 code;
213 + u8 depth;
214 + u8 csi_dt;
215 + u8 check_variants;
216 +};
217 +
218 +static const struct unicam_fmt formats[] = {
219 + /* YUV Formats */
220 + {
221 + .fourcc = V4L2_PIX_FMT_YUYV,
222 + .code = MEDIA_BUS_FMT_YUYV8_2X8,
223 + .depth = 16,
224 + .csi_dt = 0x1e,
225 + .check_variants = 1,
226 + }, {
227 + .fourcc = V4L2_PIX_FMT_UYVY,
228 + .code = MEDIA_BUS_FMT_UYVY8_2X8,
229 + .depth = 16,
230 + .csi_dt = 0x1e,
231 + .check_variants = 1,
232 + }, {
233 + .fourcc = V4L2_PIX_FMT_YVYU,
234 + .code = MEDIA_BUS_FMT_YVYU8_2X8,
235 + .depth = 16,
236 + .csi_dt = 0x1e,
237 + .check_variants = 1,
238 + }, {
239 + .fourcc = V4L2_PIX_FMT_VYUY,
240 + .code = MEDIA_BUS_FMT_VYUY8_2X8,
241 + .depth = 16,
242 + .csi_dt = 0x1e,
243 + .check_variants = 1,
244 + }, {
245 + .fourcc = V4L2_PIX_FMT_YUYV,
246 + .code = MEDIA_BUS_FMT_YUYV8_1X16,
247 + .depth = 16,
248 + .csi_dt = 0x1e,
249 + }, {
250 + .fourcc = V4L2_PIX_FMT_UYVY,
251 + .code = MEDIA_BUS_FMT_UYVY8_1X16,
252 + .depth = 16,
253 + .csi_dt = 0x1e,
254 + }, {
255 + .fourcc = V4L2_PIX_FMT_YVYU,
256 + .code = MEDIA_BUS_FMT_YVYU8_1X16,
257 + .depth = 16,
258 + .csi_dt = 0x1e,
259 + }, {
260 + .fourcc = V4L2_PIX_FMT_VYUY,
261 + .code = MEDIA_BUS_FMT_VYUY8_1X16,
262 + .depth = 16,
263 + .csi_dt = 0x1e,
264 + }, {
265 + /* RGB Formats */
266 + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
267 + .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
268 + .depth = 16,
269 + .csi_dt = 0x22,
270 + }, {
271 + .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
272 + .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
273 + .depth = 16,
274 + .csi_dt = 0x22
275 + }, {
276 + .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
277 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
278 + .depth = 16,
279 + .csi_dt = 0x21,
280 + }, {
281 + .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
282 + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
283 + .depth = 16,
284 + .csi_dt = 0x21,
285 + }, {
286 + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
287 + .code = MEDIA_BUS_FMT_RGB888_1X24,
288 + .depth = 24,
289 + .csi_dt = 0x24,
290 + }, {
291 + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
292 + .code = MEDIA_BUS_FMT_BGR888_1X24,
293 + .depth = 24,
294 + .csi_dt = 0x24,
295 + }, {
296 + .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
297 + .code = MEDIA_BUS_FMT_ARGB8888_1X32,
298 + .depth = 32,
299 + .csi_dt = 0x0,
300 + }, {
301 + /* Bayer Formats */
302 + .fourcc = V4L2_PIX_FMT_SBGGR8,
303 + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
304 + .depth = 8,
305 + .csi_dt = 0x2a,
306 + }, {
307 + .fourcc = V4L2_PIX_FMT_SGBRG8,
308 + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
309 + .depth = 8,
310 + .csi_dt = 0x2a,
311 + }, {
312 + .fourcc = V4L2_PIX_FMT_SGRBG8,
313 + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
314 + .depth = 8,
315 + .csi_dt = 0x2a,
316 + }, {
317 + .fourcc = V4L2_PIX_FMT_SRGGB8,
318 + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
319 + .depth = 8,
320 + .csi_dt = 0x2a,
321 + }, {
322 + .fourcc = V4L2_PIX_FMT_SBGGR10P,
323 + .repacked_fourcc = V4L2_PIX_FMT_SBGGR10,
324 + .code = MEDIA_BUS_FMT_SBGGR10_1X10,
325 + .depth = 10,
326 + .csi_dt = 0x2b,
327 + }, {
328 + .fourcc = V4L2_PIX_FMT_SGBRG10P,
329 + .repacked_fourcc = V4L2_PIX_FMT_SGBRG10,
330 + .code = MEDIA_BUS_FMT_SGBRG10_1X10,
331 + .depth = 10,
332 + .csi_dt = 0x2b,
333 + }, {
334 + .fourcc = V4L2_PIX_FMT_SGRBG10P,
335 + .repacked_fourcc = V4L2_PIX_FMT_SGRBG10,
336 + .code = MEDIA_BUS_FMT_SGRBG10_1X10,
337 + .depth = 10,
338 + .csi_dt = 0x2b,
339 + }, {
340 + .fourcc = V4L2_PIX_FMT_SRGGB10P,
341 + .repacked_fourcc = V4L2_PIX_FMT_SRGGB10,
342 + .code = MEDIA_BUS_FMT_SRGGB10_1X10,
343 + .depth = 10,
344 + .csi_dt = 0x2b,
345 + }, {
346 + .fourcc = V4L2_PIX_FMT_SBGGR12P,
347 + .repacked_fourcc = V4L2_PIX_FMT_SBGGR12,
348 + .code = MEDIA_BUS_FMT_SBGGR12_1X12,
349 + .depth = 12,
350 + .csi_dt = 0x2c,
351 + }, {
352 + .fourcc = V4L2_PIX_FMT_SGBRG12P,
353 + .repacked_fourcc = V4L2_PIX_FMT_SGBRG12,
354 + .code = MEDIA_BUS_FMT_SGBRG12_1X12,
355 + .depth = 12,
356 + .csi_dt = 0x2c,
357 + }, {
358 + .fourcc = V4L2_PIX_FMT_SGRBG12P,
359 + .repacked_fourcc = V4L2_PIX_FMT_SGRBG12,
360 + .code = MEDIA_BUS_FMT_SGRBG12_1X12,
361 + .depth = 12,
362 + .csi_dt = 0x2c,
363 + }, {
364 + .fourcc = V4L2_PIX_FMT_SRGGB12P,
365 + .repacked_fourcc = V4L2_PIX_FMT_SRGGB12,
366 + .code = MEDIA_BUS_FMT_SRGGB12_1X12,
367 + .depth = 12,
368 + .csi_dt = 0x2c,
369 + }, {
370 + .fourcc = V4L2_PIX_FMT_SBGGR14P,
371 + .code = MEDIA_BUS_FMT_SBGGR14_1X14,
372 + .depth = 14,
373 + .csi_dt = 0x2d,
374 + }, {
375 + .fourcc = V4L2_PIX_FMT_SGBRG14P,
376 + .code = MEDIA_BUS_FMT_SGBRG14_1X14,
377 + .depth = 14,
378 + .csi_dt = 0x2d,
379 + }, {
380 + .fourcc = V4L2_PIX_FMT_SGRBG14P,
381 + .code = MEDIA_BUS_FMT_SGRBG14_1X14,
382 + .depth = 14,
383 + .csi_dt = 0x2d,
384 + }, {
385 + .fourcc = V4L2_PIX_FMT_SRGGB14P,
386 + .code = MEDIA_BUS_FMT_SRGGB14_1X14,
387 + .depth = 14,
388 + .csi_dt = 0x2d,
389 + }, {
390 + /*
391 + * 16 bit Bayer formats could be supported, but there is no CSI2
392 + * data_type defined for raw 16, and no sensors that produce it at
393 + * present.
394 + */
395 +
396 + /* Greyscale formats */
397 + .fourcc = V4L2_PIX_FMT_GREY,
398 + .code = MEDIA_BUS_FMT_Y8_1X8,
399 + .depth = 8,
400 + .csi_dt = 0x2a,
401 + }, {
402 + .fourcc = V4L2_PIX_FMT_Y10P,
403 + .repacked_fourcc = V4L2_PIX_FMT_Y10,
404 + .code = MEDIA_BUS_FMT_Y10_1X10,
405 + .depth = 10,
406 + .csi_dt = 0x2b,
407 + }, {
408 + /* NB There is no packed V4L2 fourcc for this format. */
409 + .repacked_fourcc = V4L2_PIX_FMT_Y12,
410 + .code = MEDIA_BUS_FMT_Y12_1X12,
411 + .depth = 12,
412 + .csi_dt = 0x2c,
413 + },
414 + /* Embedded data format */
415 + {
416 + .fourcc = V4L2_META_FMT_SENSOR_DATA,
417 + .code = MEDIA_BUS_FMT_SENSOR_DATA,
418 + .depth = 8,
419 + }
420 +};
421 +
422 +struct unicam_buffer {
423 + struct vb2_v4l2_buffer vb;
424 + struct list_head list;
425 +};
426 +
427 +static inline struct unicam_buffer *to_unicam_buffer(struct vb2_buffer *vb)
428 +{
429 + return container_of(vb, struct unicam_buffer, vb.vb2_buf);
430 +}
431 +
432 +struct unicam_node {
433 + bool registered;
434 + int open;
435 + bool streaming;
436 + unsigned int pad_id;
437 + /* Pointer pointing to current v4l2_buffer */
438 + struct unicam_buffer *cur_frm;
439 + /* Pointer pointing to next v4l2_buffer */
440 + struct unicam_buffer *next_frm;
441 + /* video capture */
442 + const struct unicam_fmt *fmt;
443 + /* Used to store current pixel format */
444 + struct v4l2_format v_fmt;
445 + /* Used to store current mbus frame format */
446 + struct v4l2_mbus_framefmt m_fmt;
447 + /* Buffer queue used in video-buf */
448 + struct vb2_queue buffer_queue;
449 + /* Queue of filled frames */
450 + struct list_head dma_queue;
451 + /* IRQ lock for DMA queue */
452 + spinlock_t dma_queue_lock;
453 + /* lock used to access this structure */
454 + struct mutex lock;
455 + /* Identifies video device for this channel */
456 + struct video_device video_dev;
457 + /* Pointer to the parent handle */
458 + struct unicam_device *dev;
459 + struct media_pad pad;
460 + unsigned int embedded_lines;
461 + /*
462 + * Dummy buffer intended to be used by unicam
463 + * if we have no other queued buffers to swap to.
464 + */
465 + void *dummy_buf_cpu_addr;
466 + dma_addr_t dummy_buf_dma_addr;
467 +};
468 +
469 +struct unicam_device {
470 + struct kref kref;
471 +
472 + /* V4l2 specific parameters */
473 + struct v4l2_async_subdev asd;
474 +
475 + /* peripheral base address */
476 + void __iomem *base;
477 + /* clock gating base address */
478 + void __iomem *clk_gate_base;
479 + /* clock handle */
480 + struct clk *clock;
481 + /* V4l2 device */
482 + struct v4l2_device v4l2_dev;
483 + struct media_device mdev;
484 +
485 + /* parent device */
486 + struct platform_device *pdev;
487 + /* subdevice async Notifier */
488 + struct v4l2_async_notifier notifier;
489 + unsigned int sequence;
490 +
491 + /* ptr to sub device */
492 + struct v4l2_subdev *sensor;
493 + /* Pad config for the sensor */
494 + struct v4l2_subdev_pad_config *sensor_config;
495 +
496 + enum v4l2_mbus_type bus_type;
497 + /*
498 + * Stores bus.mipi_csi2.flags for CSI2 sensors, or
499 + * bus.mipi_csi1.strobe for CCP2.
500 + */
501 + unsigned int bus_flags;
502 + unsigned int max_data_lanes;
503 + unsigned int active_data_lanes;
504 + bool sensor_embedded_data;
505 +
506 + struct unicam_node node[MAX_NODES];
507 + struct v4l2_ctrl_handler ctrl_handler;
508 +};
509 +
510 +static inline struct unicam_device *
511 +to_unicam_device(struct v4l2_device *v4l2_dev)
512 +{
513 + return container_of(v4l2_dev, struct unicam_device, v4l2_dev);
514 +}
515 +
516 +/* Hardware access */
517 +static inline void clk_write(struct unicam_device *dev, u32 val)
518 +{
519 + writel(val | 0x5a000000, dev->clk_gate_base);
520 +}
521 +
522 +static inline u32 reg_read(struct unicam_device *dev, u32 offset)
523 +{
524 + return readl(dev->base + offset);
525 +}
526 +
527 +static inline void reg_write(struct unicam_device *dev, u32 offset, u32 val)
528 +{
529 + writel(val, dev->base + offset);
530 +}
531 +
532 +static inline int get_field(u32 value, u32 mask)
533 +{
534 + return (value & mask) >> __ffs(mask);
535 +}
536 +
537 +static inline void set_field(u32 *valp, u32 field, u32 mask)
538 +{
539 + u32 val = *valp;
540 +
541 + val &= ~mask;
542 + val |= (field << __ffs(mask)) & mask;
543 + *valp = val;
544 +}
545 +
546 +static inline u32 reg_read_field(struct unicam_device *dev, u32 offset,
547 + u32 mask)
548 +{
549 + return get_field(reg_read(dev, offset), mask);
550 +}
551 +
552 +static inline void reg_write_field(struct unicam_device *dev, u32 offset,
553 + u32 field, u32 mask)
554 +{
555 + u32 val = reg_read(dev, offset);
556 +
557 + set_field(&val, field, mask);
558 + reg_write(dev, offset, val);
559 +}
560 +
561 +/* Power management functions */
562 +static inline int unicam_runtime_get(struct unicam_device *dev)
563 +{
564 + return pm_runtime_get_sync(&dev->pdev->dev);
565 +}
566 +
567 +static inline void unicam_runtime_put(struct unicam_device *dev)
568 +{
569 + pm_runtime_put_sync(&dev->pdev->dev);
570 +}
571 +
572 +/* Format setup functions */
573 +static const struct unicam_fmt *find_format_by_code(u32 code)
574 +{
575 + unsigned int i;
576 +
577 + for (i = 0; i < ARRAY_SIZE(formats); i++) {
578 + if (formats[i].code == code)
579 + return &formats[i];
580 + }
581 +
582 + return NULL;
583 +}
584 +
585 +static int check_mbus_format(struct unicam_device *dev,
586 + const struct unicam_fmt *format)
587 +{
588 + unsigned int i;
589 + int ret = 0;
590 +
591 + for (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {
592 + struct v4l2_subdev_mbus_code_enum mbus_code = {
593 + .index = i,
594 + .pad = IMAGE_PAD,
595 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
596 + };
597 +
598 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,
599 + NULL, &mbus_code);
600 +
601 + if (!ret && mbus_code.code == format->code)
602 + return 1;
603 + }
604 +
605 + return 0;
606 +}
607 +
608 +static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,
609 + u32 pixelformat)
610 +{
611 + unsigned int i;
612 +
613 + for (i = 0; i < ARRAY_SIZE(formats); i++) {
614 + if (formats[i].fourcc == pixelformat ||
615 + formats[i].repacked_fourcc == pixelformat) {
616 + if (formats[i].check_variants &&
617 + !check_mbus_format(dev, &formats[i]))
618 + continue;
619 + return &formats[i];
620 + }
621 + }
622 +
623 + return NULL;
624 +}
625 +
626 +static inline unsigned int bytes_per_line(u32 width,
627 + const struct unicam_fmt *fmt,
628 + u32 v4l2_fourcc)
629 +{
630 + if (v4l2_fourcc == fmt->repacked_fourcc)
631 + /* Repacking always goes to 16bpp */
632 + return ALIGN(width << 1, BPL_ALIGNMENT);
633 + else
634 + return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
635 +}
636 +
637 +static int __subdev_get_format(struct unicam_device *dev,
638 + struct v4l2_mbus_framefmt *fmt, int pad_id)
639 +{
640 + struct v4l2_subdev_format sd_fmt = {
641 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
642 + .pad = pad_id
643 + };
644 + int ret;
645 +
646 + ret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,
647 + &sd_fmt);
648 + if (ret < 0)
649 + return ret;
650 +
651 + *fmt = sd_fmt.format;
652 +
653 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
654 + fmt->width, fmt->height, fmt->code);
655 +
656 + return 0;
657 +}
658 +
659 +static int __subdev_set_format(struct unicam_device *dev,
660 + struct v4l2_mbus_framefmt *fmt, int pad_id)
661 +{
662 + struct v4l2_subdev_format sd_fmt = {
663 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
664 + .pad = pad_id
665 + };
666 + int ret;
667 +
668 + sd_fmt.format = *fmt;
669 +
670 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
671 + &sd_fmt);
672 + if (ret < 0)
673 + return ret;
674 +
675 + *fmt = sd_fmt.format;
676 +
677 + if (pad_id == IMAGE_PAD)
678 + unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__, fmt->width,
679 + fmt->height, fmt->code);
680 + else
681 + unicam_dbg(1, dev, "%s Embedded data code:%04x\n", __func__,
682 + sd_fmt.format.code);
683 +
684 + return 0;
685 +}
686 +
687 +static int unicam_calc_format_size_bpl(struct unicam_device *dev,
688 + const struct unicam_fmt *fmt,
689 + struct v4l2_format *f)
690 +{
691 + unsigned int min_bytesperline;
692 +
693 + v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
694 + &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
695 + 0);
696 +
697 + min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,
698 + f->fmt.pix.pixelformat);
699 +
700 + if (f->fmt.pix.bytesperline > min_bytesperline &&
701 + f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
702 + f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
703 + BPL_ALIGNMENT);
704 + else
705 + f->fmt.pix.bytesperline = min_bytesperline;
706 +
707 + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
708 +
709 + unicam_dbg(3, dev, "%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\n",
710 + __func__,
711 + f->fmt.pix.pixelformat,
712 + f->fmt.pix.width, f->fmt.pix.height,
713 + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
714 +
715 + return 0;
716 +}
717 +
718 +static int unicam_reset_format(struct unicam_node *node)
719 +{
720 + struct unicam_device *dev = node->dev;
721 + struct v4l2_mbus_framefmt mbus_fmt;
722 + int ret;
723 +
724 + if (dev->sensor_embedded_data || node->pad_id != METADATA_PAD) {
725 + ret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);
726 + if (ret) {
727 + unicam_err(dev, "Failed to get_format - ret %d\n", ret);
728 + return ret;
729 + }
730 +
731 + if (mbus_fmt.code != node->fmt->code) {
732 + unicam_err(dev, "code mismatch - fmt->code %08x, mbus_fmt.code %08x\n",
733 + node->fmt->code, mbus_fmt.code);
734 + return ret;
735 + }
736 + }
737 +
738 + if (node->pad_id == IMAGE_PAD) {
739 + v4l2_fill_pix_format(&node->v_fmt.fmt.pix, &mbus_fmt);
740 + node->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
741 + unicam_calc_format_size_bpl(dev, node->fmt, &node->v_fmt);
742 + } else {
743 + node->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;
744 + node->v_fmt.fmt.meta.dataformat = V4L2_META_FMT_SENSOR_DATA;
745 + if (dev->sensor_embedded_data) {
746 + node->v_fmt.fmt.meta.buffersize =
747 + mbus_fmt.width * mbus_fmt.height;
748 + node->embedded_lines = mbus_fmt.height;
749 + } else {
750 + node->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;
751 + node->embedded_lines = 1;
752 + }
753 + }
754 +
755 + node->m_fmt = mbus_fmt;
756 + return 0;
757 +}
758 +
759 +static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,
760 + unsigned int buffer_size, int pad_id)
761 +{
762 + dma_addr_t endaddr = dmaaddr + buffer_size;
763 +
764 + /*
765 + * dmaaddr and endaddr should be a 32-bit address with the top two bits
766 + * set to 0x3 to signify uncached access through the Videocore memory
767 + * controller.
768 + */
769 + WARN_ON((dmaaddr >> 30) != 0x3 || (endaddr >> 30) != 0x3);
770 +
771 + if (pad_id == IMAGE_PAD) {
772 + reg_write(dev, UNICAM_IBSA0, dmaaddr);
773 + reg_write(dev, UNICAM_IBEA0, endaddr);
774 + } else {
775 + reg_write(dev, UNICAM_DBSA0, dmaaddr);
776 + reg_write(dev, UNICAM_DBEA0, endaddr);
777 + }
778 +}
779 +
780 +static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)
781 +{
782 + dma_addr_t start_addr, cur_addr;
783 + unsigned int stride = dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline;
784 + struct unicam_buffer *frm = dev->node[IMAGE_PAD].cur_frm;
785 +
786 + if (!frm)
787 + return 0;
788 +
789 + start_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);
790 + cur_addr = reg_read(dev, UNICAM_IBWP);
791 + return (unsigned int)(cur_addr - start_addr) / stride;
792 +}
793 +
794 +static inline void unicam_schedule_next_buffer(struct unicam_node *node)
795 +{
796 + struct unicam_device *dev = node->dev;
797 + struct unicam_buffer *buf;
798 + unsigned int size;
799 + dma_addr_t addr;
800 +
801 + buf = list_first_entry(&node->dma_queue, struct unicam_buffer, list);
802 + node->next_frm = buf;
803 + list_del(&buf->list);
804 +
805 + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
806 + size = (node->pad_id == IMAGE_PAD) ?
807 + node->v_fmt.fmt.pix.sizeimage :
808 + node->v_fmt.fmt.meta.buffersize;
809 +
810 + unicam_wr_dma_addr(dev, addr, size, node->pad_id);
811 +}
812 +
813 +static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)
814 +{
815 + struct unicam_device *dev = node->dev;
816 +
817 + unicam_dbg(3, dev, "Scheduling dummy buffer for node %d\n",
818 + node->pad_id);
819 +
820 + unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr, DUMMY_BUF_SIZE,
821 + node->pad_id);
822 + node->next_frm = NULL;
823 +}
824 +
825 +static inline void unicam_process_buffer_complete(struct unicam_node *node,
826 + unsigned int sequence)
827 +{
828 + node->cur_frm->vb.field = node->m_fmt.field;
829 + node->cur_frm->vb.sequence = sequence;
830 +
831 + vb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
832 +}
833 +
834 +static bool unicam_all_nodes_streaming(struct unicam_device *dev)
835 +{
836 + bool ret;
837 +
838 + ret = dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming;
839 + ret &= !dev->node[METADATA_PAD].open ||
840 + dev->node[METADATA_PAD].streaming;
841 + return ret;
842 +}
843 +
844 +static bool unicam_all_nodes_disabled(struct unicam_device *dev)
845 +{
846 + return !dev->node[IMAGE_PAD].streaming &&
847 + !dev->node[METADATA_PAD].streaming;
848 +}
849 +
850 +static void unicam_queue_event_sof(struct unicam_device *unicam)
851 +{
852 + struct v4l2_event event = {
853 + .type = V4L2_EVENT_FRAME_SYNC,
854 + .u.frame_sync.frame_sequence = unicam->sequence,
855 + };
856 +
857 + v4l2_event_queue(&unicam->node[IMAGE_PAD].video_dev, &event);
858 +}
859 +
860 +/*
861 + * unicam_isr : ISR handler for unicam capture
862 + * @irq: irq number
863 + * @dev_id: dev_id ptr
864 + *
865 + * It changes status of the captured buffer, takes next buffer from the queue
866 + * and sets its address in unicam registers
867 + */
868 +static irqreturn_t unicam_isr(int irq, void *dev)
869 +{
870 + struct unicam_device *unicam = dev;
871 + unsigned int lines_done = unicam_get_lines_done(dev);
872 + unsigned int sequence = unicam->sequence;
873 + unsigned int i;
874 + u32 ista, sta;
875 + u64 ts;
876 +
877 + /*
878 + * Don't service interrupts if not streaming.
879 + * Avoids issues if the VPU should enable the
880 + * peripheral without the kernel knowing (that
881 + * shouldn't happen, but causes issues if it does).
882 + */
883 + if (unicam_all_nodes_disabled(unicam))
884 + return IRQ_NONE;
885 +
886 + sta = reg_read(unicam, UNICAM_STA);
887 + /* Write value back to clear the interrupts */
888 + reg_write(unicam, UNICAM_STA, sta);
889 +
890 + ista = reg_read(unicam, UNICAM_ISTA);
891 + /* Write value back to clear the interrupts */
892 + reg_write(unicam, UNICAM_ISTA, ista);
893 +
894 + unicam_dbg(3, unicam, "ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d",
895 + ista, sta, sequence, lines_done);
896 +
897 + if (!(sta & (UNICAM_IS | UNICAM_PI0)))
898 + return IRQ_HANDLED;
899 +
900 + /*
901 + * We must run the frame end handler first. If we have a valid next_frm
902 + * and we get a simultaneout FE + FS interrupt, running the FS handler
903 + * first would null out the next_frm ptr and we would have lost the
904 + * buffer forever.
905 + */
906 + if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
907 + /*
908 + * Ensure we have swapped buffers already as we can't
909 + * stop the peripheral. If no buffer is available, use a
910 + * dummy buffer to dump out frames until we get a new buffer
911 + * to use.
912 + */
913 + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
914 + if (!unicam->node[i].streaming)
915 + continue;
916 +
917 + if (unicam->node[i].cur_frm)
918 + unicam_process_buffer_complete(&unicam->node[i],
919 + sequence);
920 + unicam->node[i].cur_frm = unicam->node[i].next_frm;
921 + }
922 + unicam->sequence++;
923 + }
924 +
925 + if (ista & UNICAM_FSI) {
926 + /*
927 + * Timestamp is to be when the first data byte was captured,
928 + * aka frame start.
929 + */
930 + ts = ktime_get_ns();
931 + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
932 + if (!unicam->node[i].streaming)
933 + continue;
934 +
935 + if (unicam->node[i].cur_frm)
936 + unicam->node[i].cur_frm->vb.vb2_buf.timestamp =
937 + ts;
938 + /*
939 + * Set the next frame output to go to a dummy frame
940 + * if we have not managed to obtain another frame
941 + * from the queue.
942 + */
943 + unicam_schedule_dummy_buffer(&unicam->node[i]);
944 + }
945 +
946 + unicam_queue_event_sof(unicam);
947 + }
948 +
949 + /*
950 + * Cannot swap buffer at frame end, there may be a race condition
951 + * where the HW does not actually swap it if the new frame has
952 + * already started.
953 + */
954 + if (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {
955 + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
956 + if (!unicam->node[i].streaming)
957 + continue;
958 +
959 + spin_lock(&unicam->node[i].dma_queue_lock);
960 + if (!list_empty(&unicam->node[i].dma_queue) &&
961 + !unicam->node[i].next_frm)
962 + unicam_schedule_next_buffer(&unicam->node[i]);
963 + spin_unlock(&unicam->node[i].dma_queue_lock);
964 + }
965 + }
966 +
967 + if (reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {
968 + /* Switch out of trigger mode if selected */
969 + reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
970 + reg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);
971 + }
972 + return IRQ_HANDLED;
973 +}
974 +
975 +static int unicam_querycap(struct file *file, void *priv,
976 + struct v4l2_capability *cap)
977 +{
978 + struct unicam_node *node = video_drvdata(file);
979 + struct unicam_device *dev = node->dev;
980 +
981 + strlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
982 + strlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
983 +
984 + snprintf(cap->bus_info, sizeof(cap->bus_info),
985 + "platform:%s", dev_name(&dev->pdev->dev));
986 +
987 + cap->capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_META_CAPTURE;
988 +
989 + return 0;
990 +}
991 +
992 +static int unicam_enum_fmt_vid_cap(struct file *file, void *priv,
993 + struct v4l2_fmtdesc *f)
994 +{
995 + struct unicam_node *node = video_drvdata(file);
996 + struct unicam_device *dev = node->dev;
997 + unsigned int index = 0;
998 + unsigned int i;
999 + int ret = 0;
1000 +
1001 + if (node->pad_id != IMAGE_PAD)
1002 + return -EINVAL;
1003 +
1004 + for (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {
1005 + struct v4l2_subdev_mbus_code_enum mbus_code = {
1006 + .index = i,
1007 + .pad = IMAGE_PAD,
1008 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1009 + };
1010 + const struct unicam_fmt *fmt;
1011 +
1012 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,
1013 + NULL, &mbus_code);
1014 + if (ret < 0) {
1015 + unicam_dbg(2, dev,
1016 + "subdev->enum_mbus_code idx %d returned %d - index invalid\n",
1017 + i, ret);
1018 + return -EINVAL;
1019 + }
1020 +
1021 + fmt = find_format_by_code(mbus_code.code);
1022 + if (fmt) {
1023 + if (fmt->fourcc) {
1024 + if (index == f->index) {
1025 + f->pixelformat = fmt->fourcc;
1026 + break;
1027 + }
1028 + index++;
1029 + }
1030 + if (fmt->repacked_fourcc) {
1031 + if (index == f->index) {
1032 + f->pixelformat = fmt->repacked_fourcc;
1033 + break;
1034 + }
1035 + index++;
1036 + }
1037 + }
1038 + }
1039 +
1040 + return 0;
1041 +}
1042 +
1043 +static int unicam_g_fmt_vid_cap(struct file *file, void *priv,
1044 + struct v4l2_format *f)
1045 +{
1046 + struct v4l2_mbus_framefmt mbus_fmt = {0};
1047 + struct unicam_node *node = video_drvdata(file);
1048 + struct unicam_device *dev = node->dev;
1049 + const struct unicam_fmt *fmt = NULL;
1050 + int ret;
1051 +
1052 + if (node->pad_id != IMAGE_PAD)
1053 + return -EINVAL;
1054 +
1055 + /*
1056 + * If a flip has occurred in the sensor, the fmt code might have
1057 + * changed. So we will need to re-fetch the format from the subdevice.
1058 + */
1059 + ret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);
1060 + if (ret)
1061 + return -EINVAL;
1062 +
1063 + /* Find the V4L2 format from mbus code. We must match a known format. */
1064 + fmt = find_format_by_code(mbus_fmt.code);
1065 + if (!fmt)
1066 + return -EINVAL;
1067 +
1068 + node->fmt = fmt;
1069 + node->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1070 + *f = node->v_fmt;
1071 +
1072 + return 0;
1073 +}
1074 +
1075 +static
1076 +const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)
1077 +{
1078 + struct v4l2_subdev_mbus_code_enum mbus_code;
1079 + const struct unicam_fmt *fmt = NULL;
1080 + unsigned int i;
1081 + int ret;
1082 +
1083 + for (i = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++i) {
1084 + memset(&mbus_code, 0, sizeof(mbus_code));
1085 + mbus_code.index = i;
1086 + mbus_code.pad = IMAGE_PAD;
1087 + mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1088 +
1089 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,
1090 + &mbus_code);
1091 + if (ret < 0) {
1092 + unicam_dbg(2, dev,
1093 + "subdev->enum_mbus_code idx %u returned %d - continue\n",
1094 + i, ret);
1095 + continue;
1096 + }
1097 +
1098 + unicam_dbg(2, dev, "subdev %s: code: 0x%08x idx: %u\n",
1099 + dev->sensor->name, mbus_code.code, i);
1100 +
1101 + fmt = find_format_by_code(mbus_code.code);
1102 + unicam_dbg(2, dev, "fmt 0x%08x returned as %p, V4L2 FOURCC 0x%08x, csi_dt 0x%02x\n",
1103 + mbus_code.code, fmt, fmt ? fmt->fourcc : 0,
1104 + fmt ? fmt->csi_dt : 0);
1105 + if (fmt)
1106 + return fmt;
1107 + }
1108 +
1109 + return NULL;
1110 +}
1111 +
1112 +static int unicam_try_fmt_vid_cap(struct file *file, void *priv,
1113 + struct v4l2_format *f)
1114 +{
1115 + struct unicam_node *node = video_drvdata(file);
1116 + struct unicam_device *dev = node->dev;
1117 + struct v4l2_subdev_format sd_fmt = {
1118 + .which = V4L2_SUBDEV_FORMAT_TRY,
1119 + .pad = IMAGE_PAD
1120 + };
1121 + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
1122 + const struct unicam_fmt *fmt;
1123 + int ret;
1124 +
1125 + if (node->pad_id != IMAGE_PAD)
1126 + return -EINVAL;
1127 +
1128 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
1129 + if (!fmt) {
1130 + /*
1131 + * Pixel format not supported by unicam. Choose the first
1132 + * supported format, and let the sensor choose something else.
1133 + */
1134 + unicam_dbg(3, dev, "Fourcc format (0x%08x) not found. Use first format.\n",
1135 + f->fmt.pix.pixelformat);
1136 +
1137 + fmt = &formats[0];
1138 + f->fmt.pix.pixelformat = fmt->fourcc;
1139 + }
1140 +
1141 + v4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);
1142 + /*
1143 + * No support for receiving interlaced video, so never
1144 + * request it from the sensor subdev.
1145 + */
1146 + mbus_fmt->field = V4L2_FIELD_NONE;
1147 +
1148 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
1149 + &sd_fmt);
1150 + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
1151 + return ret;
1152 +
1153 + if (mbus_fmt->field != V4L2_FIELD_NONE)
1154 + unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
1155 +
1156 + v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
1157 + if (mbus_fmt->code != fmt->code) {
1158 + /* Sensor has returned an alternate format */
1159 + fmt = find_format_by_code(mbus_fmt->code);
1160 + if (!fmt) {
1161 + /*
1162 + * The alternate format is one unicam can't support.
1163 + * Find the first format that is supported by both, and
1164 + * then set that.
1165 + */
1166 + fmt = get_first_supported_format(dev);
1167 + mbus_fmt->code = fmt->code;
1168 +
1169 + ret = v4l2_subdev_call(dev->sensor, pad, set_fmt,
1170 + dev->sensor_config, &sd_fmt);
1171 + if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
1172 + return ret;
1173 +
1174 + if (mbus_fmt->field != V4L2_FIELD_NONE)
1175 + unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
1176 +
1177 + v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
1178 +
1179 + if (mbus_fmt->code != fmt->code) {
1180 + /*
1181 + * We've set a format that the sensor reports
1182 + * as being supported, but it refuses to set it.
1183 + * Not much else we can do.
1184 + * Assume that the sensor driver may accept the
1185 + * format when it is set (rather than tried).
1186 + */
1187 + unicam_err(dev, "Sensor won't accept default format, and Unicam can't support sensor default\n");
1188 + }
1189 + }
1190 +
1191 + if (fmt->fourcc)
1192 + f->fmt.pix.pixelformat = fmt->fourcc;
1193 + else
1194 + f->fmt.pix.pixelformat = fmt->repacked_fourcc;
1195 + }
1196 +
1197 + return unicam_calc_format_size_bpl(dev, fmt, f);
1198 +}
1199 +
1200 +static int unicam_s_fmt_vid_cap(struct file *file, void *priv,
1201 + struct v4l2_format *f)
1202 +{
1203 + struct unicam_node *node = video_drvdata(file);
1204 + struct unicam_device *dev = node->dev;
1205 + struct vb2_queue *q = &node->buffer_queue;
1206 + struct v4l2_mbus_framefmt mbus_fmt = {0};
1207 + const struct unicam_fmt *fmt;
1208 + int ret;
1209 +
1210 + if (vb2_is_busy(q))
1211 + return -EBUSY;
1212 +
1213 + ret = unicam_try_fmt_vid_cap(file, priv, f);
1214 + if (ret < 0)
1215 + return ret;
1216 +
1217 + fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
1218 + if (!fmt) {
1219 + /*
1220 + * Unknown pixel format - adopt a default.
1221 + * This shouldn't happen as try_fmt should have resolved any
1222 + * issues first.
1223 + */
1224 + fmt = get_first_supported_format(dev);
1225 + if (!fmt)
1226 + /*
1227 + * It shouldn't be possible to get here with no
1228 + * supported formats
1229 + */
1230 + return -EINVAL;
1231 + f->fmt.pix.pixelformat = fmt->fourcc;
1232 + return -EINVAL;
1233 + }
1234 +
1235 + v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
1236 +
1237 + ret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);
1238 + if (ret) {
1239 + unicam_dbg(3, dev, "%s __subdev_set_format failed %d\n",
1240 + __func__, ret);
1241 + return ret;
1242 + }
1243 +
1244 + /* Just double check nothing has gone wrong */
1245 + if (mbus_fmt.code != fmt->code) {
1246 + unicam_dbg(3, dev,
1247 + "%s subdev changed format on us, this should not happen\n",
1248 + __func__);
1249 + return -EINVAL;
1250 + }
1251 +
1252 + node->fmt = fmt;
1253 + node->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
1254 + node->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
1255 + unicam_reset_format(node);
1256 +
1257 + unicam_dbg(3, dev,
1258 + "%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\n",
1259 + __func__, node->v_fmt.fmt.pix.width,
1260 + node->v_fmt.fmt.pix.height, mbus_fmt.code,
1261 + node->v_fmt.fmt.pix.pixelformat);
1262 +
1263 + *f = node->v_fmt;
1264 +
1265 + return 0;
1266 +}
1267 +
1268 +static int unicam_enum_fmt_meta_cap(struct file *file, void *priv,
1269 + struct v4l2_fmtdesc *f)
1270 +{
1271 + struct unicam_node *node = video_drvdata(file);
1272 + struct unicam_device *dev = node->dev;
1273 + const struct unicam_fmt *fmt;
1274 + u32 code;
1275 + int ret = 0;
1276 +
1277 + if (node->pad_id != METADATA_PAD || f->index != 0)
1278 + return -EINVAL;
1279 +
1280 + if (dev->sensor_embedded_data) {
1281 + struct v4l2_subdev_mbus_code_enum mbus_code = {
1282 + .index = f->index,
1283 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1284 + .pad = METADATA_PAD,
1285 + };
1286 +
1287 + ret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,
1288 + &mbus_code);
1289 + if (ret < 0) {
1290 + unicam_dbg(2, dev,
1291 + "subdev->enum_mbus_code idx 0 returned %d - index invalid\n",
1292 + ret);
1293 + return -EINVAL;
1294 + }
1295 +
1296 + code = mbus_code.code;
1297 + } else {
1298 + code = MEDIA_BUS_FMT_SENSOR_DATA;
1299 + }
1300 +
1301 + fmt = find_format_by_code(code);
1302 + if (fmt)
1303 + f->pixelformat = fmt->fourcc;
1304 +
1305 + return 0;
1306 +}
1307 +
1308 +static int unicam_g_fmt_meta_cap(struct file *file, void *priv,
1309 + struct v4l2_format *f)
1310 +{
1311 + struct unicam_node *node = video_drvdata(file);
1312 +
1313 + if (node->pad_id != METADATA_PAD)
1314 + return -EINVAL;
1315 +
1316 + *f = node->v_fmt;
1317 +
1318 + return 0;
1319 +}
1320 +
1321 +static int unicam_queue_setup(struct vb2_queue *vq,
1322 + unsigned int *nbuffers,
1323 + unsigned int *nplanes,
1324 + unsigned int sizes[],
1325 + struct device *alloc_devs[])
1326 +{
1327 + struct unicam_node *node = vb2_get_drv_priv(vq);
1328 + struct unicam_device *dev = node->dev;
1329 + unsigned int size = node->pad_id == IMAGE_PAD ?
1330 + node->v_fmt.fmt.pix.sizeimage :
1331 + node->v_fmt.fmt.meta.buffersize;
1332 +
1333 + if (vq->num_buffers + *nbuffers < 3)
1334 + *nbuffers = 3 - vq->num_buffers;
1335 +
1336 + if (*nplanes) {
1337 + if (sizes[0] < size) {
1338 + unicam_err(dev, "sizes[0] %i < size %u\n", sizes[0],
1339 + size);
1340 + return -EINVAL;
1341 + }
1342 + size = sizes[0];
1343 + }
1344 +
1345 + *nplanes = 1;
1346 + sizes[0] = size;
1347 +
1348 + return 0;
1349 +}
1350 +
1351 +static int unicam_buffer_prepare(struct vb2_buffer *vb)
1352 +{
1353 + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
1354 + struct unicam_device *dev = node->dev;
1355 + struct unicam_buffer *buf = to_unicam_buffer(vb);
1356 + unsigned long size;
1357 +
1358 + if (WARN_ON(!node->fmt))
1359 + return -EINVAL;
1360 +
1361 + size = node->pad_id == IMAGE_PAD ? node->v_fmt.fmt.pix.sizeimage :
1362 + node->v_fmt.fmt.meta.buffersize;
1363 + if (vb2_plane_size(vb, 0) < size) {
1364 + unicam_err(dev, "data will not fit into plane (%lu < %lu)\n",
1365 + vb2_plane_size(vb, 0), size);
1366 + return -EINVAL;
1367 + }
1368 +
1369 + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1370 + return 0;
1371 +}
1372 +
1373 +static void unicam_buffer_queue(struct vb2_buffer *vb)
1374 +{
1375 + struct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);
1376 + struct unicam_buffer *buf = to_unicam_buffer(vb);
1377 + unsigned long flags;
1378 +
1379 + spin_lock_irqsave(&node->dma_queue_lock, flags);
1380 + list_add_tail(&buf->list, &node->dma_queue);
1381 + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
1382 +}
1383 +
1384 +static void unicam_set_packing_config(struct unicam_device *dev)
1385 +{
1386 + u32 pack, unpack;
1387 + u32 val;
1388 +
1389 + if (dev->node[IMAGE_PAD].v_fmt.fmt.pix.pixelformat ==
1390 + dev->node[IMAGE_PAD].fmt->fourcc) {
1391 + unpack = UNICAM_PUM_NONE;
1392 + pack = UNICAM_PPM_NONE;
1393 + } else {
1394 + switch (dev->node[IMAGE_PAD].fmt->depth) {
1395 + case 8:
1396 + unpack = UNICAM_PUM_UNPACK8;
1397 + break;
1398 + case 10:
1399 + unpack = UNICAM_PUM_UNPACK10;
1400 + break;
1401 + case 12:
1402 + unpack = UNICAM_PUM_UNPACK12;
1403 + break;
1404 + case 14:
1405 + unpack = UNICAM_PUM_UNPACK14;
1406 + break;
1407 + case 16:
1408 + unpack = UNICAM_PUM_UNPACK16;
1409 + break;
1410 + default:
1411 + unpack = UNICAM_PUM_NONE;
1412 + break;
1413 + }
1414 +
1415 + /* Repacking is always to 16bpp */
1416 + pack = UNICAM_PPM_PACK16;
1417 + }
1418 +
1419 + val = 0;
1420 + set_field(&val, unpack, UNICAM_PUM_MASK);
1421 + set_field(&val, pack, UNICAM_PPM_MASK);
1422 + reg_write(dev, UNICAM_IPIPE, val);
1423 +}
1424 +
1425 +static void unicam_cfg_image_id(struct unicam_device *dev)
1426 +{
1427 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1428 + /* CSI2 mode, hardcode VC 0 for now. */
1429 + reg_write(dev, UNICAM_IDI0,
1430 + (0 << 6) | dev->node[IMAGE_PAD].fmt->csi_dt);
1431 + } else {
1432 + /* CCP2 mode */
1433 + reg_write(dev, UNICAM_IDI0,
1434 + 0x80 | dev->node[IMAGE_PAD].fmt->csi_dt);
1435 + }
1436 +}
1437 +
1438 +static void unicam_enable_ed(struct unicam_device *dev)
1439 +{
1440 + u32 val = reg_read(dev, UNICAM_DCS);
1441 +
1442 + set_field(&val, 2, UNICAM_EDL_MASK);
1443 + /* Do not wrap at the end of the embedded data buffer */
1444 + set_field(&val, 0, UNICAM_DBOB);
1445 +
1446 + reg_write(dev, UNICAM_DCS, val);
1447 +}
1448 +
1449 +static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)
1450 +{
1451 + int line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;
1452 + unsigned int size, i;
1453 + u32 val;
1454 +
1455 + if (line_int_freq < 128)
1456 + line_int_freq = 128;
1457 +
1458 + /* Enable lane clocks */
1459 + val = 1;
1460 + for (i = 0; i < dev->active_data_lanes; i++)
1461 + val = val << 2 | 1;
1462 + clk_write(dev, val);
1463 +
1464 + /* Basic init */
1465 + reg_write(dev, UNICAM_CTRL, UNICAM_MEM);
1466 +
1467 + /* Enable analogue control, and leave in reset. */
1468 + val = UNICAM_AR;
1469 + set_field(&val, 7, UNICAM_CTATADJ_MASK);
1470 + set_field(&val, 7, UNICAM_PTATADJ_MASK);
1471 + reg_write(dev, UNICAM_ANA, val);
1472 + usleep_range(1000, 2000);
1473 +
1474 + /* Come out of reset */
1475 + reg_write_field(dev, UNICAM_ANA, 0, UNICAM_AR);
1476 +
1477 + /* Peripheral reset */
1478 + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
1479 + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
1480 +
1481 + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
1482 +
1483 + /* Enable Rx control. */
1484 + val = reg_read(dev, UNICAM_CTRL);
1485 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1486 + set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
1487 + set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
1488 + } else {
1489 + set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
1490 + set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
1491 + }
1492 + /* Packet framer timeout */
1493 + set_field(&val, 0xf, UNICAM_PFT_MASK);
1494 + set_field(&val, 128, UNICAM_OET_MASK);
1495 + reg_write(dev, UNICAM_CTRL, val);
1496 +
1497 + reg_write(dev, UNICAM_IHWIN, 0);
1498 + reg_write(dev, UNICAM_IVWIN, 0);
1499 +
1500 + /* AXI bus access QoS setup */
1501 + val = reg_read(dev, UNICAM_PRI);
1502 + set_field(&val, 0, UNICAM_BL_MASK);
1503 + set_field(&val, 0, UNICAM_BS_MASK);
1504 + set_field(&val, 0xe, UNICAM_PP_MASK);
1505 + set_field(&val, 8, UNICAM_NP_MASK);
1506 + set_field(&val, 2, UNICAM_PT_MASK);
1507 + set_field(&val, 1, UNICAM_PE);
1508 + reg_write(dev, UNICAM_PRI, val);
1509 +
1510 + reg_write_field(dev, UNICAM_ANA, 0, UNICAM_DDL);
1511 +
1512 + /* Always start in trigger frame capture mode (UNICAM_FCM set) */
1513 + val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
1514 + set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
1515 + reg_write(dev, UNICAM_ICTL, val);
1516 + reg_write(dev, UNICAM_STA, UNICAM_STA_MASK_ALL);
1517 + reg_write(dev, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
1518 +
1519 + /* tclk_term_en */
1520 + reg_write_field(dev, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
1521 + /* tclk_settle */
1522 + reg_write_field(dev, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
1523 + /* td_term_en */
1524 + reg_write_field(dev, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
1525 + /* ths_settle */
1526 + reg_write_field(dev, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
1527 + /* trx_enable */
1528 + reg_write_field(dev, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
1529 +
1530 + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_SOE);
1531 +
1532 + /* Packet compare setup - required to avoid missing frame ends */
1533 + val = 0;
1534 + set_field(&val, 1, UNICAM_PCE);
1535 + set_field(&val, 1, UNICAM_GI);
1536 + set_field(&val, 1, UNICAM_CPH);
1537 + set_field(&val, 0, UNICAM_PCVC_MASK);
1538 + set_field(&val, 1, UNICAM_PCDT_MASK);
1539 + reg_write(dev, UNICAM_CMP0, val);
1540 +
1541 + /* Enable clock lane and set up terminations */
1542 + val = 0;
1543 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1544 + /* CSI2 */
1545 + set_field(&val, 1, UNICAM_CLE);
1546 + set_field(&val, 1, UNICAM_CLLPE);
1547 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1548 + set_field(&val, 1, UNICAM_CLTRE);
1549 + set_field(&val, 1, UNICAM_CLHSE);
1550 + }
1551 + } else {
1552 + /* CCP2 */
1553 + set_field(&val, 1, UNICAM_CLE);
1554 + set_field(&val, 1, UNICAM_CLHSE);
1555 + set_field(&val, 1, UNICAM_CLTRE);
1556 + }
1557 + reg_write(dev, UNICAM_CLK, val);
1558 +
1559 + /*
1560 + * Enable required data lanes with appropriate terminations.
1561 + * The same value needs to be written to UNICAM_DATn registers for
1562 + * the active lanes, and 0 for inactive ones.
1563 + */
1564 + val = 0;
1565 + if (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {
1566 + /* CSI2 */
1567 + set_field(&val, 1, UNICAM_DLE);
1568 + set_field(&val, 1, UNICAM_DLLPE);
1569 + if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
1570 + set_field(&val, 1, UNICAM_DLTRE);
1571 + set_field(&val, 1, UNICAM_DLHSE);
1572 + }
1573 + } else {
1574 + /* CCP2 */
1575 + set_field(&val, 1, UNICAM_DLE);
1576 + set_field(&val, 1, UNICAM_DLHSE);
1577 + set_field(&val, 1, UNICAM_DLTRE);
1578 + }
1579 + reg_write(dev, UNICAM_DAT0, val);
1580 +
1581 + if (dev->active_data_lanes == 1)
1582 + val = 0;
1583 + reg_write(dev, UNICAM_DAT1, val);
1584 +
1585 + if (dev->max_data_lanes > 2) {
1586 + /*
1587 + * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
1588 + * instance supports more than 2 data lanes.
1589 + */
1590 + if (dev->active_data_lanes == 2)
1591 + val = 0;
1592 + reg_write(dev, UNICAM_DAT2, val);
1593 +
1594 + if (dev->active_data_lanes == 3)
1595 + val = 0;
1596 + reg_write(dev, UNICAM_DAT3, val);
1597 + }
1598 +
1599 + reg_write(dev, UNICAM_IBLS,
1600 + dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);
1601 + size = dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;
1602 + unicam_wr_dma_addr(dev, addr[IMAGE_PAD], size, IMAGE_PAD);
1603 + unicam_set_packing_config(dev);
1604 + unicam_cfg_image_id(dev);
1605 +
1606 + val = reg_read(dev, UNICAM_MISC);
1607 + set_field(&val, 1, UNICAM_FL0);
1608 + set_field(&val, 1, UNICAM_FL1);
1609 + reg_write(dev, UNICAM_MISC, val);
1610 +
1611 + if (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {
1612 + size = dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;
1613 + unicam_enable_ed(dev);
1614 + unicam_wr_dma_addr(dev, addr[METADATA_PAD], size, METADATA_PAD);
1615 + }
1616 +
1617 + /* Enable peripheral */
1618 + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPE);
1619 +
1620 + /* Load image pointers */
1621 + reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
1622 +
1623 + /* Load embedded data buffer pointers if needed */
1624 + if (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data)
1625 + reg_write_field(dev, UNICAM_DCS, 1, UNICAM_LDP);
1626 +
1627 + /*
1628 + * Enable trigger only for the first frame to
1629 + * sync correctly to the FS from the source.
1630 + */
1631 + reg_write_field(dev, UNICAM_ICTL, 1, UNICAM_TFC);
1632 +}
1633 +
1634 +static void unicam_disable(struct unicam_device *dev)
1635 +{
1636 + /* Analogue lane control disable */
1637 + reg_write_field(dev, UNICAM_ANA, 1, UNICAM_DDL);
1638 +
1639 + /* Stop the output engine */
1640 + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_SOE);
1641 +
1642 + /* Disable the data lanes. */
1643 + reg_write(dev, UNICAM_DAT0, 0);
1644 + reg_write(dev, UNICAM_DAT1, 0);
1645 +
1646 + if (dev->max_data_lanes > 2) {
1647 + reg_write(dev, UNICAM_DAT2, 0);
1648 + reg_write(dev, UNICAM_DAT3, 0);
1649 + }
1650 +
1651 + /* Peripheral reset */
1652 + reg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);
1653 + usleep_range(50, 100);
1654 + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);
1655 +
1656 + /* Disable peripheral */
1657 + reg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);
1658 +
1659 + /* Clear ED setup */
1660 + reg_write(dev, UNICAM_DCS, 0);
1661 +
1662 + /* Disable all lane clocks */
1663 + clk_write(dev, 0);
1664 +}
1665 +
1666 +static void unicam_return_buffers(struct unicam_node *node)
1667 +{
1668 + struct unicam_buffer *buf, *tmp;
1669 + unsigned long flags;
1670 +
1671 + spin_lock_irqsave(&node->dma_queue_lock, flags);
1672 + list_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {
1673 + list_del(&buf->list);
1674 + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1675 + }
1676 +
1677 + if (node->cur_frm)
1678 + vb2_buffer_done(&node->cur_frm->vb.vb2_buf,
1679 + VB2_BUF_STATE_ERROR);
1680 + if (node->next_frm && node->cur_frm != node->next_frm)
1681 + vb2_buffer_done(&node->next_frm->vb.vb2_buf,
1682 + VB2_BUF_STATE_ERROR);
1683 +
1684 + node->cur_frm = NULL;
1685 + node->next_frm = NULL;
1686 + spin_unlock_irqrestore(&node->dma_queue_lock, flags);
1687 +}
1688 +
1689 +static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
1690 +{
1691 + struct unicam_node *node = vb2_get_drv_priv(vq);
1692 + struct unicam_device *dev = node->dev;
1693 + dma_addr_t buffer_addr[MAX_NODES] = { 0 };
1694 + unsigned long flags;
1695 + unsigned int i;
1696 + int ret;
1697 +
1698 + node->streaming = true;
1699 + if (!unicam_all_nodes_streaming(dev)) {
1700 + unicam_dbg(3, dev, "Not all nodes are streaming yet.");
1701 + return 0;
1702 + }
1703 +
1704 + dev->sequence = 0;
1705 + ret = unicam_runtime_get(dev);
1706 + if (ret < 0) {
1707 + unicam_dbg(3, dev, "unicam_runtime_get failed\n");
1708 + goto err_streaming;
1709 + }
1710 +
1711 + /*
1712 + * TODO: Retrieve the number of active data lanes from the connected
1713 + * subdevice.
1714 + */
1715 + dev->active_data_lanes = dev->max_data_lanes;
1716 +
1717 + ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
1718 + if (ret) {
1719 + unicam_err(dev, "failed to set up clock\n");
1720 + goto err_pm_put;
1721 + }
1722 +
1723 + ret = clk_prepare_enable(dev->clock);
1724 + if (ret) {
1725 + unicam_err(dev, "Failed to enable CSI clock: %d\n", ret);
1726 + goto err_pm_put;
1727 + }
1728 +
1729 + for (i = 0; i < ARRAY_SIZE(dev->node); i++) {
1730 + struct unicam_buffer *buf;
1731 +
1732 + if (!dev->node[i].streaming)
1733 + continue;
1734 +
1735 + spin_lock_irqsave(&dev->node[i].dma_queue_lock, flags);
1736 + buf = list_first_entry(&dev->node[i].dma_queue,
1737 + struct unicam_buffer, list);
1738 + dev->node[i].cur_frm = buf;
1739 + dev->node[i].next_frm = buf;
1740 + list_del(&buf->list);
1741 + spin_unlock_irqrestore(&dev->node[i].dma_queue_lock, flags);
1742 +
1743 + buffer_addr[i] =
1744 + vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
1745 + }
1746 +
1747 + unicam_start_rx(dev, buffer_addr);
1748 +
1749 + ret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);
1750 + if (ret < 0) {
1751 + unicam_err(dev, "stream on failed in subdev\n");
1752 + goto err_disable_unicam;
1753 + }
1754 +
1755 + return 0;
1756 +
1757 +err_disable_unicam:
1758 + unicam_disable(dev);
1759 + clk_disable_unprepare(dev->clock);
1760 +err_pm_put:
1761 + unicam_runtime_put(dev);
1762 +err_streaming:
1763 + unicam_return_buffers(node);
1764 + node->streaming = false;
1765 +
1766 + return ret;
1767 +}
1768 +
1769 +static void unicam_stop_streaming(struct vb2_queue *vq)
1770 +{
1771 + struct unicam_node *node = vb2_get_drv_priv(vq);
1772 + struct unicam_device *dev = node->dev;
1773 +
1774 + node->streaming = false;
1775 +
1776 + if (node->pad_id == IMAGE_PAD) {
1777 + /*
1778 + * Stop streaming the sensor and disable the peripheral.
1779 + * We cannot continue streaming embedded data with the
1780 + * image pad disabled.
1781 + */
1782 + if (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)
1783 + unicam_err(dev, "stream off failed in subdev\n");
1784 +
1785 + unicam_disable(dev);
1786 + clk_disable_unprepare(dev->clock);
1787 + unicam_runtime_put(dev);
1788 +
1789 + } else if (node->pad_id == METADATA_PAD) {
1790 + /*
1791 + * Allow the hardware to spin in the dummy buffer.
1792 + * This is only really needed if the embedded data pad is
1793 + * disabled before the image pad.
1794 + */
1795 + unicam_wr_dma_addr(dev, node->dummy_buf_dma_addr,
1796 + DUMMY_BUF_SIZE, METADATA_PAD);
1797 + }
1798 +
1799 + /* Clear all queued buffers for the node */
1800 + unicam_return_buffers(node);
1801 +}
1802 +
1803 +static int unicam_enum_input(struct file *file, void *priv,
1804 + struct v4l2_input *inp)
1805 +{
1806 + struct unicam_node *node = video_drvdata(file);
1807 + struct unicam_device *dev = node->dev;
1808 +
1809 + if (inp->index != 0)
1810 + return -EINVAL;
1811 +
1812 + inp->type = V4L2_INPUT_TYPE_CAMERA;
1813 + if (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {
1814 + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
1815 + inp->std = 0;
1816 + } else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {
1817 + inp->capabilities = V4L2_IN_CAP_STD;
1818 + if (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)
1819 + < 0)
1820 + inp->std = V4L2_STD_ALL;
1821 + } else {
1822 + inp->capabilities = 0;
1823 + inp->std = 0;
1824 + }
1825 + sprintf(inp->name, "Camera 0");
1826 + return 0;
1827 +}
1828 +
1829 +static int unicam_g_input(struct file *file, void *priv, unsigned int *i)
1830 +{
1831 + *i = 0;
1832 +
1833 + return 0;
1834 +}
1835 +
1836 +static int unicam_s_input(struct file *file, void *priv, unsigned int i)
1837 +{
1838 + /*
1839 + * FIXME: Ideally we would like to be able to query the source
1840 + * subdevice for information over the input connectors it supports,
1841 + * and map that through in to a call to video_ops->s_routing.
1842 + * There is no infrastructure support for defining that within
1843 + * devicetree at present. Until that is implemented we can't
1844 + * map a user physical connector number to s_routing input number.
1845 + */
1846 + if (i > 0)
1847 + return -EINVAL;
1848 +
1849 + return 0;
1850 +}
1851 +
1852 +static int unicam_querystd(struct file *file, void *priv,
1853 + v4l2_std_id *std)
1854 +{
1855 + struct unicam_node *node = video_drvdata(file);
1856 + struct unicam_device *dev = node->dev;
1857 +
1858 + return v4l2_subdev_call(dev->sensor, video, querystd, std);
1859 +}
1860 +
1861 +static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)
1862 +{
1863 + struct unicam_node *node = video_drvdata(file);
1864 + struct unicam_device *dev = node->dev;
1865 +
1866 + return v4l2_subdev_call(dev->sensor, video, g_std, std);
1867 +}
1868 +
1869 +static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)
1870 +{
1871 + struct unicam_node *node = video_drvdata(file);
1872 + struct unicam_device *dev = node->dev;
1873 + int ret;
1874 + v4l2_std_id current_std;
1875 +
1876 + ret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);
1877 + if (ret)
1878 + return ret;
1879 +
1880 + if (std == current_std)
1881 + return 0;
1882 +
1883 + if (vb2_is_busy(&node->buffer_queue))
1884 + return -EBUSY;
1885 +
1886 + ret = v4l2_subdev_call(dev->sensor, video, s_std, std);
1887 +
1888 + /* Force recomputation of bytesperline */
1889 + node->v_fmt.fmt.pix.bytesperline = 0;
1890 +
1891 + unicam_reset_format(node);
1892 +
1893 + return ret;
1894 +}
1895 +
1896 +static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1897 +{
1898 + struct unicam_node *node = video_drvdata(file);
1899 + struct unicam_device *dev = node->dev;
1900 +
1901 + return v4l2_subdev_call(dev->sensor, pad, set_edid, edid);
1902 +}
1903 +
1904 +static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)
1905 +{
1906 + struct unicam_node *node = video_drvdata(file);
1907 + struct unicam_device *dev = node->dev;
1908 +
1909 + return v4l2_subdev_call(dev->sensor, pad, get_edid, edid);
1910 +}
1911 +
1912 +static int unicam_s_selection(struct file *file, void *priv,
1913 + struct v4l2_selection *sel)
1914 +{
1915 + struct unicam_node *node = video_drvdata(file);
1916 + struct unicam_device *dev = node->dev;
1917 + struct v4l2_subdev_selection sdsel = {
1918 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1919 + .target = sel->target,
1920 + .flags = sel->flags,
1921 + .r = sel->r,
1922 + };
1923 +
1924 + return v4l2_subdev_call(dev->sensor, pad, set_selection, NULL, &sdsel);
1925 +}
1926 +
1927 +static int unicam_g_selection(struct file *file, void *priv,
1928 + struct v4l2_selection *sel)
1929 +{
1930 + struct unicam_node *node = video_drvdata(file);
1931 + struct unicam_device *dev = node->dev;
1932 + struct v4l2_subdev_selection sdsel = {
1933 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1934 + .target = sel->target,
1935 + };
1936 + int ret;
1937 +
1938 + ret = v4l2_subdev_call(dev->sensor, pad, get_selection, NULL, &sdsel);
1939 + if (!ret)
1940 + sel->r = sdsel.r;
1941 +
1942 + return ret;
1943 +}
1944 +
1945 +static int unicam_enum_framesizes(struct file *file, void *priv,
1946 + struct v4l2_frmsizeenum *fsize)
1947 +{
1948 + struct unicam_node *node = video_drvdata(file);
1949 + struct unicam_device *dev = node->dev;
1950 + const struct unicam_fmt *fmt;
1951 + struct v4l2_subdev_frame_size_enum fse;
1952 + int ret;
1953 +
1954 + /* check for valid format */
1955 + fmt = find_format_by_pix(dev, fsize->pixel_format);
1956 + if (!fmt) {
1957 + unicam_dbg(3, dev, "Invalid pixel code: %x\n",
1958 + fsize->pixel_format);
1959 + return -EINVAL;
1960 + }
1961 + fse.code = fmt->code;
1962 +
1963 + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1964 + fse.index = fsize->index;
1965 + fse.pad = node->pad_id;
1966 +
1967 + ret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);
1968 + if (ret)
1969 + return ret;
1970 +
1971 + unicam_dbg(1, dev, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
1972 + __func__, fse.index, fse.code, fse.min_width, fse.max_width,
1973 + fse.min_height, fse.max_height);
1974 +
1975 + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1976 + fsize->discrete.width = fse.max_width;
1977 + fsize->discrete.height = fse.max_height;
1978 +
1979 + return 0;
1980 +}
1981 +
1982 +static int unicam_enum_frameintervals(struct file *file, void *priv,
1983 + struct v4l2_frmivalenum *fival)
1984 +{
1985 + struct unicam_node *node = video_drvdata(file);
1986 + struct unicam_device *dev = node->dev;
1987 + const struct unicam_fmt *fmt;
1988 + struct v4l2_subdev_frame_interval_enum fie = {
1989 + .index = fival->index,
1990 + .width = fival->width,
1991 + .height = fival->height,
1992 + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1993 + };
1994 + int ret;
1995 +
1996 + fmt = find_format_by_pix(dev, fival->pixel_format);
1997 + if (!fmt)
1998 + return -EINVAL;
1999 +
2000 + fie.code = fmt->code;
2001 + ret = v4l2_subdev_call(dev->sensor, pad, enum_frame_interval,
2002 + NULL, &fie);
2003 + if (ret)
2004 + return ret;
2005 +
2006 + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
2007 + fival->discrete = fie.interval;
2008 +
2009 + return 0;
2010 +}
2011 +
2012 +static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
2013 +{
2014 + struct unicam_node *node = video_drvdata(file);
2015 + struct unicam_device *dev = node->dev;
2016 +
2017 + return v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);
2018 +}
2019 +
2020 +static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
2021 +{
2022 + struct unicam_node *node = video_drvdata(file);
2023 + struct unicam_device *dev = node->dev;
2024 +
2025 + return v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);
2026 +}
2027 +
2028 +static int unicam_g_dv_timings(struct file *file, void *priv,
2029 + struct v4l2_dv_timings *timings)
2030 +{
2031 + struct unicam_node *node = video_drvdata(file);
2032 + struct unicam_device *dev = node->dev;
2033 +
2034 + return v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);
2035 +}
2036 +
2037 +static int unicam_s_dv_timings(struct file *file, void *priv,
2038 + struct v4l2_dv_timings *timings)
2039 +{
2040 + struct unicam_node *node = video_drvdata(file);
2041 + struct unicam_device *dev = node->dev;
2042 + struct v4l2_dv_timings current_timings;
2043 + int ret;
2044 +
2045 + ret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,
2046 + &current_timings);
2047 +
2048 + if (v4l2_match_dv_timings(timings, &current_timings, 0, false))
2049 + return 0;
2050 +
2051 + if (vb2_is_busy(&node->buffer_queue))
2052 + return -EBUSY;
2053 +
2054 + ret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);
2055 +
2056 + /* Force recomputation of bytesperline */
2057 + node->v_fmt.fmt.pix.bytesperline = 0;
2058 +
2059 + unicam_reset_format(node);
2060 +
2061 + return ret;
2062 +}
2063 +
2064 +static int unicam_query_dv_timings(struct file *file, void *priv,
2065 + struct v4l2_dv_timings *timings)
2066 +{
2067 + struct unicam_node *node = video_drvdata(file);
2068 + struct unicam_device *dev = node->dev;
2069 +
2070 + return v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);
2071 +}
2072 +
2073 +static int unicam_enum_dv_timings(struct file *file, void *priv,
2074 + struct v4l2_enum_dv_timings *timings)
2075 +{
2076 + struct unicam_node *node = video_drvdata(file);
2077 + struct unicam_device *dev = node->dev;
2078 +
2079 + return v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);
2080 +}
2081 +
2082 +static int unicam_dv_timings_cap(struct file *file, void *priv,
2083 + struct v4l2_dv_timings_cap *cap)
2084 +{
2085 + struct unicam_node *node = video_drvdata(file);
2086 + struct unicam_device *dev = node->dev;
2087 +
2088 + return v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);
2089 +}
2090 +
2091 +static int unicam_subscribe_event(struct v4l2_fh *fh,
2092 + const struct v4l2_event_subscription *sub)
2093 +{
2094 + switch (sub->type) {
2095 + case V4L2_EVENT_FRAME_SYNC:
2096 + return v4l2_event_subscribe(fh, sub, 2, NULL);
2097 + case V4L2_EVENT_SOURCE_CHANGE:
2098 + return v4l2_event_subscribe(fh, sub, 4, NULL);
2099 + }
2100 +
2101 + return v4l2_ctrl_subscribe_event(fh, sub);
2102 +}
2103 +
2104 +static int unicam_log_status(struct file *file, void *fh)
2105 +{
2106 + struct unicam_node *node = video_drvdata(file);
2107 + struct unicam_device *dev = node->dev;
2108 + u32 reg;
2109 +
2110 + /* status for sub devices */
2111 + v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
2112 +
2113 + unicam_info(dev, "-----Receiver status-----\n");
2114 + unicam_info(dev, "V4L2 width/height: %ux%u\n",
2115 + node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);
2116 + unicam_info(dev, "Mediabus format: %08x\n", node->fmt->code);
2117 + unicam_info(dev, "V4L2 format: %08x\n",
2118 + node->v_fmt.fmt.pix.pixelformat);
2119 + reg = reg_read(dev, UNICAM_IPIPE);
2120 + unicam_info(dev, "Unpacking/packing: %u / %u\n",
2121 + get_field(reg, UNICAM_PUM_MASK),
2122 + get_field(reg, UNICAM_PPM_MASK));
2123 + unicam_info(dev, "----Live data----\n");
2124 + unicam_info(dev, "Programmed stride: %4u\n",
2125 + reg_read(dev, UNICAM_IBLS));
2126 + unicam_info(dev, "Detected resolution: %ux%u\n",
2127 + reg_read(dev, UNICAM_IHSTA),
2128 + reg_read(dev, UNICAM_IVSTA));
2129 + unicam_info(dev, "Write pointer: %08x\n",
2130 + reg_read(dev, UNICAM_IBWP));
2131 +
2132 + return 0;
2133 +}
2134 +
2135 +static void unicam_notify(struct v4l2_subdev *sd,
2136 + unsigned int notification, void *arg)
2137 +{
2138 + struct unicam_device *dev = to_unicam_device(sd->v4l2_dev);
2139 +
2140 + switch (notification) {
2141 + case V4L2_DEVICE_NOTIFY_EVENT:
2142 + v4l2_event_queue(&dev->node[IMAGE_PAD].video_dev, arg);
2143 + break;
2144 + default:
2145 + break;
2146 + }
2147 +}
2148 +
2149 +static const struct vb2_ops unicam_video_qops = {
2150 + .wait_prepare = vb2_ops_wait_prepare,
2151 + .wait_finish = vb2_ops_wait_finish,
2152 + .queue_setup = unicam_queue_setup,
2153 + .buf_prepare = unicam_buffer_prepare,
2154 + .buf_queue = unicam_buffer_queue,
2155 + .start_streaming = unicam_start_streaming,
2156 + .stop_streaming = unicam_stop_streaming,
2157 +};
2158 +
2159 +/*
2160 + * unicam_v4l2_open : This function is based on the v4l2_fh_open helper
2161 + * function. It has been augmented to handle sensor subdevice power management,
2162 + */
2163 +static int unicam_v4l2_open(struct file *file)
2164 +{
2165 + struct unicam_node *node = video_drvdata(file);
2166 + struct unicam_device *dev = node->dev;
2167 + int ret;
2168 +
2169 + mutex_lock(&node->lock);
2170 +
2171 + ret = v4l2_fh_open(file);
2172 + if (ret) {
2173 + unicam_err(dev, "v4l2_fh_open failed\n");
2174 + goto unlock;
2175 + }
2176 +
2177 + node->open++;
2178 +
2179 + if (!v4l2_fh_is_singular_file(file))
2180 + goto unlock;
2181 +
2182 + ret = v4l2_subdev_call(dev->sensor, core, s_power, 1);
2183 + if (ret < 0 && ret != -ENOIOCTLCMD) {
2184 + v4l2_fh_release(file);
2185 + node->open--;
2186 + goto unlock;
2187 + }
2188 +
2189 + ret = 0;
2190 +
2191 +unlock:
2192 + mutex_unlock(&node->lock);
2193 + return ret;
2194 +}
2195 +
2196 +static int unicam_v4l2_release(struct file *file)
2197 +{
2198 + struct unicam_node *node = video_drvdata(file);
2199 + struct unicam_device *dev = node->dev;
2200 + struct v4l2_subdev *sd = dev->sensor;
2201 + bool fh_singular;
2202 + int ret;
2203 +
2204 + mutex_lock(&node->lock);
2205 +
2206 + fh_singular = v4l2_fh_is_singular_file(file);
2207 +
2208 + ret = _vb2_fop_release(file, NULL);
2209 +
2210 + if (fh_singular)
2211 + v4l2_subdev_call(sd, core, s_power, 0);
2212 +
2213 + node->open--;
2214 + mutex_unlock(&node->lock);
2215 +
2216 + return ret;
2217 +}
2218 +
2219 +/* unicam capture driver file operations */
2220 +static const struct v4l2_file_operations unicam_fops = {
2221 + .owner = THIS_MODULE,
2222 + .open = unicam_v4l2_open,
2223 + .release = unicam_v4l2_release,
2224 + .read = vb2_fop_read,
2225 + .poll = vb2_fop_poll,
2226 + .unlocked_ioctl = video_ioctl2,
2227 + .mmap = vb2_fop_mmap,
2228 +};
2229 +
2230 +/* unicam capture ioctl operations */
2231 +static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
2232 + .vidioc_querycap = unicam_querycap,
2233 + .vidioc_enum_fmt_vid_cap = unicam_enum_fmt_vid_cap,
2234 + .vidioc_g_fmt_vid_cap = unicam_g_fmt_vid_cap,
2235 + .vidioc_s_fmt_vid_cap = unicam_s_fmt_vid_cap,
2236 + .vidioc_try_fmt_vid_cap = unicam_try_fmt_vid_cap,
2237 +
2238 + .vidioc_enum_fmt_meta_cap = unicam_enum_fmt_meta_cap,
2239 + .vidioc_g_fmt_meta_cap = unicam_g_fmt_meta_cap,
2240 + .vidioc_s_fmt_meta_cap = unicam_g_fmt_meta_cap,
2241 + .vidioc_try_fmt_meta_cap = unicam_g_fmt_meta_cap,
2242 +
2243 + .vidioc_enum_input = unicam_enum_input,
2244 + .vidioc_g_input = unicam_g_input,
2245 + .vidioc_s_input = unicam_s_input,
2246 +
2247 + .vidioc_querystd = unicam_querystd,
2248 + .vidioc_s_std = unicam_s_std,
2249 + .vidioc_g_std = unicam_g_std,
2250 +
2251 + .vidioc_g_edid = unicam_g_edid,
2252 + .vidioc_s_edid = unicam_s_edid,
2253 +
2254 + .vidioc_enum_framesizes = unicam_enum_framesizes,
2255 + .vidioc_enum_frameintervals = unicam_enum_frameintervals,
2256 +
2257 + .vidioc_g_selection = unicam_g_selection,
2258 + .vidioc_s_selection = unicam_s_selection,
2259 +
2260 + .vidioc_g_parm = unicam_g_parm,
2261 + .vidioc_s_parm = unicam_s_parm,
2262 +
2263 + .vidioc_s_dv_timings = unicam_s_dv_timings,
2264 + .vidioc_g_dv_timings = unicam_g_dv_timings,
2265 + .vidioc_query_dv_timings = unicam_query_dv_timings,
2266 + .vidioc_enum_dv_timings = unicam_enum_dv_timings,
2267 + .vidioc_dv_timings_cap = unicam_dv_timings_cap,
2268 +
2269 + .vidioc_reqbufs = vb2_ioctl_reqbufs,
2270 + .vidioc_create_bufs = vb2_ioctl_create_bufs,
2271 + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
2272 + .vidioc_querybuf = vb2_ioctl_querybuf,
2273 + .vidioc_qbuf = vb2_ioctl_qbuf,
2274 + .vidioc_dqbuf = vb2_ioctl_dqbuf,
2275 + .vidioc_expbuf = vb2_ioctl_expbuf,
2276 + .vidioc_streamon = vb2_ioctl_streamon,
2277 + .vidioc_streamoff = vb2_ioctl_streamoff,
2278 +
2279 + .vidioc_log_status = unicam_log_status,
2280 + .vidioc_subscribe_event = unicam_subscribe_event,
2281 + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2282 +};
2283 +
2284 +static int
2285 +unicam_async_bound(struct v4l2_async_notifier *notifier,
2286 + struct v4l2_subdev *subdev,
2287 + struct v4l2_async_subdev *asd)
2288 +{
2289 + struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
2290 +
2291 + if (unicam->sensor) {
2292 + unicam_info(unicam, "Rejecting subdev %s (Already set!!)",
2293 + subdev->name);
2294 + return 0;
2295 + }
2296 +
2297 + unicam->sensor = subdev;
2298 + unicam_dbg(1, unicam, "Using sensor %s for capture\n", subdev->name);
2299 +
2300 + return 0;
2301 +}
2302 +
2303 +static void unicam_release(struct kref *kref)
2304 +{
2305 + struct unicam_device *unicam =
2306 + container_of(kref, struct unicam_device, kref);
2307 +
2308 + v4l2_ctrl_handler_free(&unicam->ctrl_handler);
2309 + media_device_cleanup(&unicam->mdev);
2310 +
2311 + if (unicam->sensor_config)
2312 + v4l2_subdev_free_pad_config(unicam->sensor_config);
2313 +
2314 + kfree(unicam);
2315 +}
2316 +
2317 +static void unicam_put(struct unicam_device *unicam)
2318 +{
2319 + kref_put(&unicam->kref, unicam_release);
2320 +}
2321 +
2322 +static void unicam_get(struct unicam_device *unicam)
2323 +{
2324 + kref_get(&unicam->kref);
2325 +}
2326 +
2327 +static void unicam_node_release(struct video_device *vdev)
2328 +{
2329 + struct unicam_node *node = video_get_drvdata(vdev);
2330 +
2331 + unicam_put(node->dev);
2332 +}
2333 +
2334 +static int register_node(struct unicam_device *unicam, struct unicam_node *node,
2335 + enum v4l2_buf_type type, int pad_id)
2336 +{
2337 + struct video_device *vdev;
2338 + struct vb2_queue *q;
2339 + struct v4l2_mbus_framefmt mbus_fmt = {0};
2340 + const struct unicam_fmt *fmt;
2341 + int ret;
2342 +
2343 + if (pad_id == IMAGE_PAD) {
2344 + ret = __subdev_get_format(unicam, &mbus_fmt, pad_id);
2345 + if (ret) {
2346 + unicam_err(unicam, "Failed to get_format - ret %d\n",
2347 + ret);
2348 + return ret;
2349 + }
2350 +
2351 + fmt = find_format_by_code(mbus_fmt.code);
2352 + if (!fmt) {
2353 + /*
2354 + * Find the first format that the sensor and unicam both
2355 + * support
2356 + */
2357 + fmt = get_first_supported_format(unicam);
2358 +
2359 + if (!fmt)
2360 + /* No compatible formats */
2361 + return -EINVAL;
2362 +
2363 + mbus_fmt.code = fmt->code;
2364 + ret = __subdev_set_format(unicam, &mbus_fmt, pad_id);
2365 + if (ret)
2366 + return -EINVAL;
2367 + }
2368 + if (mbus_fmt.field != V4L2_FIELD_NONE) {
2369 + /* Interlaced not supported - disable it now. */
2370 + mbus_fmt.field = V4L2_FIELD_NONE;
2371 + ret = __subdev_set_format(unicam, &mbus_fmt, pad_id);
2372 + if (ret)
2373 + return -EINVAL;
2374 + }
2375 +
2376 + node->v_fmt.fmt.pix.pixelformat = fmt->fourcc ? fmt->fourcc
2377 + : fmt->repacked_fourcc;
2378 + } else {
2379 + /* Fix this node format as embedded data. */
2380 + fmt = find_format_by_code(MEDIA_BUS_FMT_SENSOR_DATA);
2381 + node->v_fmt.fmt.meta.dataformat = fmt->fourcc;
2382 + }
2383 +
2384 + node->dev = unicam;
2385 + node->pad_id = pad_id;
2386 + node->fmt = fmt;
2387 +
2388 + /* Read current subdev format */
2389 + unicam_reset_format(node);
2390 +
2391 + if (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
2392 + v4l2_std_id tvnorms;
2393 +
2394 + if (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,
2395 + g_tvnorms)))
2396 + /*
2397 + * Subdevice should not advertise s_std but not
2398 + * g_tvnorms
2399 + */
2400 + return -EINVAL;
2401 +
2402 + ret = v4l2_subdev_call(unicam->sensor, video,
2403 + g_tvnorms, &tvnorms);
2404 + if (WARN_ON(ret))
2405 + return -EINVAL;
2406 + node->video_dev.tvnorms |= tvnorms;
2407 + }
2408 +
2409 + spin_lock_init(&node->dma_queue_lock);
2410 + mutex_init(&node->lock);
2411 +
2412 + vdev = &node->video_dev;
2413 + if (pad_id == IMAGE_PAD) {
2414 + /* Add controls from the subdevice */
2415 + ret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,
2416 + unicam->sensor->ctrl_handler, NULL,
2417 + true);
2418 + if (ret < 0)
2419 + return ret;
2420 +
2421 + /*
2422 + * If the sensor subdevice has any controls, associate the node
2423 + * with the ctrl handler to allow access from userland.
2424 + */
2425 + if (!list_empty(&unicam->ctrl_handler.ctrls))
2426 + vdev->ctrl_handler = &unicam->ctrl_handler;
2427 + }
2428 +
2429 + q = &node->buffer_queue;
2430 + q->type = type;
2431 + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
2432 + q->drv_priv = node;
2433 + q->ops = &unicam_video_qops;
2434 + q->mem_ops = &vb2_dma_contig_memops;
2435 + q->buf_struct_size = sizeof(struct unicam_buffer);
2436 + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2437 + q->lock = &node->lock;
2438 + q->min_buffers_needed = 2;
2439 + q->dev = &unicam->pdev->dev;
2440 +
2441 + ret = vb2_queue_init(q);
2442 + if (ret) {
2443 + unicam_err(unicam, "vb2_queue_init() failed\n");
2444 + return ret;
2445 + }
2446 +
2447 + INIT_LIST_HEAD(&node->dma_queue);
2448 +
2449 + vdev->release = unicam_node_release;
2450 + vdev->fops = &unicam_fops;
2451 + vdev->ioctl_ops = &unicam_ioctl_ops;
2452 + vdev->v4l2_dev = &unicam->v4l2_dev;
2453 + vdev->vfl_dir = VFL_DIR_RX;
2454 + vdev->queue = q;
2455 + vdev->lock = &node->lock;
2456 + vdev->device_caps = (pad_id == IMAGE_PAD) ?
2457 + (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING) :
2458 + (V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING);
2459 +
2460 + /* Define the device names */
2461 + snprintf(vdev->name, sizeof(vdev->name), "%s-%s", UNICAM_MODULE_NAME,
2462 + pad_id == IMAGE_PAD ? "image" : "embedded");
2463 +
2464 + video_set_drvdata(vdev, node);
2465 + if (pad_id == IMAGE_PAD)
2466 + vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
2467 + node->pad.flags = MEDIA_PAD_FL_SINK;
2468 + media_entity_pads_init(&vdev->entity, 1, &node->pad);
2469 +
2470 + node->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,
2471 + DUMMY_BUF_SIZE,
2472 + &node->dummy_buf_dma_addr,
2473 + GFP_KERNEL);
2474 + if (!node->dummy_buf_cpu_addr) {
2475 + unicam_err(unicam, "Unable to allocate dummy buffer.\n");
2476 + return -ENOMEM;
2477 + }
2478 +
2479 + if (pad_id == METADATA_PAD) {
2480 + v4l2_disable_ioctl(vdev, VIDIOC_DQEVENT);
2481 + v4l2_disable_ioctl(vdev, VIDIOC_SUBSCRIBE_EVENT);
2482 + v4l2_disable_ioctl(vdev, VIDIOC_UNSUBSCRIBE_EVENT);
2483 + }
2484 + if (pad_id == METADATA_PAD ||
2485 + !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
2486 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);
2487 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_G_STD);
2488 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUMSTD);
2489 + }
2490 + if (pad_id == METADATA_PAD ||
2491 + !v4l2_subdev_has_op(unicam->sensor, video, querystd))
2492 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERYSTD);
2493 + if (pad_id == METADATA_PAD ||
2494 + !v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {
2495 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_EDID);
2496 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_G_EDID);
2497 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_DV_TIMINGS_CAP);
2498 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_G_DV_TIMINGS);
2499 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_DV_TIMINGS);
2500 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_DV_TIMINGS);
2501 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERY_DV_TIMINGS);
2502 + }
2503 + if (pad_id == METADATA_PAD ||
2504 + !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))
2505 + v4l2_disable_ioctl(&node->video_dev,
2506 + VIDIOC_ENUM_FRAMEINTERVALS);
2507 + if (pad_id == METADATA_PAD ||
2508 + !v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))
2509 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_G_PARM);
2510 + if (pad_id == METADATA_PAD ||
2511 + !v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))
2512 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_PARM);
2513 +
2514 + if (pad_id == METADATA_PAD ||
2515 + !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))
2516 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);
2517 +
2518 + if (node->pad_id == METADATA_PAD ||
2519 + !v4l2_subdev_has_op(unicam->sensor, pad, set_selection))
2520 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_SELECTION);
2521 +
2522 + if (node->pad_id == METADATA_PAD ||
2523 + !v4l2_subdev_has_op(unicam->sensor, pad, get_selection))
2524 + v4l2_disable_ioctl(&node->video_dev, VIDIOC_G_SELECTION);
2525 +
2526 + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
2527 + if (ret) {
2528 + unicam_err(unicam, "Unable to register video device %s\n",
2529 + vdev->name);
2530 + return ret;
2531 + }
2532 +
2533 + /*
2534 + * Acquire a reference to unicam, which will be released when the video
2535 + * device will be unregistered and userspace will have closed all open
2536 + * file handles.
2537 + */
2538 + unicam_get(unicam);
2539 + node->registered = true;
2540 +
2541 + if (pad_id != METADATA_PAD || unicam->sensor_embedded_data) {
2542 + ret = media_create_pad_link(&unicam->sensor->entity, pad_id,
2543 + &node->video_dev.entity, 0,
2544 + MEDIA_LNK_FL_ENABLED |
2545 + MEDIA_LNK_FL_IMMUTABLE);
2546 + if (ret)
2547 + unicam_err(unicam, "Unable to create pad link for %s\n",
2548 + vdev->name);
2549 + }
2550 +
2551 + return ret;
2552 +}
2553 +
2554 +static void unregister_nodes(struct unicam_device *unicam)
2555 +{
2556 + unsigned int i;
2557 +
2558 + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) {
2559 + struct unicam_node *node = &unicam->node[i];
2560 +
2561 + if (node->dummy_buf_cpu_addr) {
2562 + dma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,
2563 + node->dummy_buf_cpu_addr,
2564 + node->dummy_buf_dma_addr);
2565 + }
2566 +
2567 + if (node->registered) {
2568 + node->registered = false;
2569 + video_unregister_device(&node->video_dev);
2570 + }
2571 + }
2572 +}
2573 +
2574 +static int unicam_probe_complete(struct unicam_device *unicam)
2575 +{
2576 + int ret;
2577 +
2578 + unicam->v4l2_dev.notify = unicam_notify;
2579 +
2580 + unicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);
2581 + if (!unicam->sensor_config)
2582 + return -ENOMEM;
2583 +
2584 + unicam->sensor_embedded_data = (unicam->sensor->entity.num_pads >= 2);
2585 +
2586 + ret = register_node(unicam, &unicam->node[IMAGE_PAD],
2587 + V4L2_BUF_TYPE_VIDEO_CAPTURE, IMAGE_PAD);
2588 + if (ret) {
2589 + unicam_err(unicam, "Unable to register image video device.\n");
2590 + goto unregister;
2591 + }
2592 +
2593 + ret = register_node(unicam, &unicam->node[METADATA_PAD],
2594 + V4L2_BUF_TYPE_META_CAPTURE, METADATA_PAD);
2595 + if (ret) {
2596 + unicam_err(unicam, "Unable to register metadata video device.\n");
2597 + goto unregister;
2598 + }
2599 +
2600 + ret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);
2601 + if (ret) {
2602 + unicam_err(unicam, "Unable to register subdev nodes.\n");
2603 + goto unregister;
2604 + }
2605 +
2606 + /*
2607 + * Release the initial reference, all references are now owned by the
2608 + * video devices.
2609 + */
2610 + unicam_put(unicam);
2611 + return 0;
2612 +
2613 +unregister:
2614 + unregister_nodes(unicam);
2615 + unicam_put(unicam);
2616 +
2617 + return ret;
2618 +}
2619 +
2620 +static int unicam_async_complete(struct v4l2_async_notifier *notifier)
2621 +{
2622 + struct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);
2623 +
2624 + return unicam_probe_complete(unicam);
2625 +}
2626 +
2627 +static const struct v4l2_async_notifier_operations unicam_async_ops = {
2628 + .bound = unicam_async_bound,
2629 + .complete = unicam_async_complete,
2630 +};
2631 +
2632 +static int of_unicam_connect_subdevs(struct unicam_device *dev)
2633 +{
2634 + struct platform_device *pdev = dev->pdev;
2635 + struct v4l2_fwnode_endpoint ep = { 0 };
2636 + struct device_node *ep_node;
2637 + struct device_node *sensor_node;
2638 + unsigned int lane;
2639 + int ret = -EINVAL;
2640 +
2641 + if (of_property_read_u32(pdev->dev.of_node, "brcm,num-data-lanes",
2642 + &dev->max_data_lanes) < 0) {
2643 + unicam_err(dev, "number of data lanes not set\n");
2644 + return -EINVAL;
2645 + }
2646 +
2647 + /* Get the local endpoint and remote device. */
2648 + ep_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
2649 + if (!ep_node) {
2650 + unicam_dbg(3, dev, "can't get next endpoint\n");
2651 + return -EINVAL;
2652 + }
2653 +
2654 + unicam_dbg(3, dev, "ep_node is %pOF\n", ep_node);
2655 +
2656 + sensor_node = of_graph_get_remote_port_parent(ep_node);
2657 + if (!sensor_node) {
2658 + unicam_dbg(3, dev, "can't get remote parent\n");
2659 + goto cleanup_exit;
2660 + }
2661 +
2662 + unicam_dbg(1, dev, "found subdevice %pOF\n", sensor_node);
2663 +
2664 + /* Parse the local endpoint and validate its configuration. */
2665 + v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
2666 +
2667 + unicam_dbg(3, dev, "parsed local endpoint, bus_type %u\n",
2668 + ep.bus_type);
2669 +
2670 + dev->bus_type = ep.bus_type;
2671 +
2672 + switch (ep.bus_type) {
2673 + case V4L2_MBUS_CSI2_DPHY:
2674 + switch (ep.bus.mipi_csi2.num_data_lanes) {
2675 + case 1:
2676 + case 2:
2677 + case 4:
2678 + break;
2679 +
2680 + default:
2681 + unicam_err(dev, "subdevice %pOF: %u data lanes not supported\n",
2682 + sensor_node,
2683 + ep.bus.mipi_csi2.num_data_lanes);
2684 + goto cleanup_exit;
2685 + }
2686 +
2687 + for (lane = 0; lane < ep.bus.mipi_csi2.num_data_lanes; lane++) {
2688 + if (ep.bus.mipi_csi2.data_lanes[lane] != lane + 1) {
2689 + unicam_err(dev, "subdevice %pOF: data lanes reordering not supported\n",
2690 + sensor_node);
2691 + goto cleanup_exit;
2692 + }
2693 + }
2694 +
2695 + if (ep.bus.mipi_csi2.num_data_lanes > dev->max_data_lanes) {
2696 + unicam_err(dev, "subdevice requires %u data lanes when %u are supported\n",
2697 + ep.bus.mipi_csi2.num_data_lanes,
2698 + dev->max_data_lanes);
2699 + }
2700 +
2701 + dev->max_data_lanes = ep.bus.mipi_csi2.num_data_lanes;
2702 + dev->bus_flags = ep.bus.mipi_csi2.flags;
2703 +
2704 + break;
2705 +
2706 + case V4L2_MBUS_CCP2:
2707 + if (ep.bus.mipi_csi1.clock_lane != 0 ||
2708 + ep.bus.mipi_csi1.data_lane != 1) {
2709 + unicam_err(dev, "subdevice %pOF: unsupported lanes configuration\n",
2710 + sensor_node);
2711 + goto cleanup_exit;
2712 + }
2713 +
2714 + dev->max_data_lanes = 1;
2715 + dev->bus_flags = ep.bus.mipi_csi1.strobe;
2716 + break;
2717 +
2718 + default:
2719 + /* Unsupported bus type */
2720 + unicam_err(dev, "subdevice %pOF: unsupported bus type %u\n",
2721 + sensor_node, ep.bus_type);
2722 + goto cleanup_exit;
2723 + }
2724 +
2725 + unicam_dbg(3, dev, "subdevice %pOF: %s bus, %u data lanes, flags=0x%08x\n",
2726 + sensor_node,
2727 + dev->bus_type == V4L2_MBUS_CSI2_DPHY ? "CSI-2" : "CCP2",
2728 + dev->max_data_lanes, dev->bus_flags);
2729 +
2730 + /* Initialize and register the async notifier. */
2731 + v4l2_async_notifier_init(&dev->notifier);
2732 + dev->notifier.ops = &unicam_async_ops;
2733 +
2734 + dev->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
2735 + dev->asd.match.fwnode = of_fwnode_handle(sensor_node);
2736 + ret = v4l2_async_notifier_add_subdev(&dev->notifier, &dev->asd);
2737 + if (ret) {
2738 + unicam_err(dev, "Error adding subdevice: %d\n", ret);
2739 + goto cleanup_exit;
2740 + }
2741 +
2742 + ret = v4l2_async_notifier_register(&dev->v4l2_dev, &dev->notifier);
2743 + if (ret) {
2744 + unicam_err(dev, "Error registering async notifier: %d\n", ret);
2745 + ret = -EINVAL;
2746 + }
2747 +
2748 +cleanup_exit:
2749 + of_node_put(sensor_node);
2750 + of_node_put(ep_node);
2751 +
2752 + return ret;
2753 +}
2754 +
2755 +static int unicam_probe(struct platform_device *pdev)
2756 +{
2757 + struct unicam_device *unicam;
2758 + int ret;
2759 +
2760 + unicam = kzalloc(sizeof(*unicam), GFP_KERNEL);
2761 + if (!unicam)
2762 + return -ENOMEM;
2763 +
2764 + kref_init(&unicam->kref);
2765 + unicam->pdev = pdev;
2766 +
2767 + unicam->base = devm_platform_ioremap_resource(pdev, 0);
2768 + if (IS_ERR(unicam->base)) {
2769 + unicam_err(unicam, "Failed to get main io block\n");
2770 + ret = PTR_ERR(unicam->base);
2771 + goto err_unicam_put;
2772 + }
2773 +
2774 + unicam->clk_gate_base = devm_platform_ioremap_resource(pdev, 1);
2775 + if (IS_ERR(unicam->clk_gate_base)) {
2776 + unicam_err(unicam, "Failed to get 2nd io block\n");
2777 + ret = PTR_ERR(unicam->clk_gate_base);
2778 + goto err_unicam_put;
2779 + }
2780 +
2781 + unicam->clock = devm_clk_get(&pdev->dev, "lp");
2782 + if (IS_ERR(unicam->clock)) {
2783 + unicam_err(unicam, "Failed to get clock\n");
2784 + ret = PTR_ERR(unicam->clock);
2785 + goto err_unicam_put;
2786 + }
2787 +
2788 + ret = platform_get_irq(pdev, 0);
2789 + if (ret <= 0) {
2790 + dev_err(&pdev->dev, "No IRQ resource\n");
2791 + ret = -EINVAL;
2792 + goto err_unicam_put;
2793 + }
2794 +
2795 + ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
2796 + "unicam_capture0", unicam);
2797 + if (ret) {
2798 + dev_err(&pdev->dev, "Unable to request interrupt\n");
2799 + ret = -EINVAL;
2800 + goto err_unicam_put;
2801 + }
2802 +
2803 + unicam->mdev.dev = &pdev->dev;
2804 + strscpy(unicam->mdev.model, UNICAM_MODULE_NAME,
2805 + sizeof(unicam->mdev.model));
2806 + strscpy(unicam->mdev.serial, "", sizeof(unicam->mdev.serial));
2807 + snprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),
2808 + "platform:%s", dev_name(&pdev->dev));
2809 + unicam->mdev.hw_revision = 0;
2810 +
2811 + media_device_init(&unicam->mdev);
2812 +
2813 + unicam->v4l2_dev.mdev = &unicam->mdev;
2814 +
2815 + ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
2816 + if (ret) {
2817 + unicam_err(unicam,
2818 + "Unable to register v4l2 device.\n");
2819 + goto err_unicam_put;
2820 + }
2821 +
2822 + ret = media_device_register(&unicam->mdev);
2823 + if (ret < 0) {
2824 + unicam_err(unicam,
2825 + "Unable to register media-controller device.\n");
2826 + goto err_v4l2_unregister;
2827 + }
2828 +
2829 + /* Reserve space for the controls */
2830 + ret = v4l2_ctrl_handler_init(&unicam->ctrl_handler, 16);
2831 + if (ret < 0)
2832 + goto err_media_unregister;
2833 +
2834 + /* set the driver data in platform device */
2835 + platform_set_drvdata(pdev, unicam);
2836 +
2837 + ret = of_unicam_connect_subdevs(unicam);
2838 + if (ret) {
2839 + dev_err(&pdev->dev, "Failed to connect subdevs\n");
2840 + goto err_media_unregister;
2841 + }
2842 +
2843 + /* Enable the block power domain */
2844 + pm_runtime_enable(&pdev->dev);
2845 +
2846 + return 0;
2847 +
2848 +err_media_unregister:
2849 + media_device_unregister(&unicam->mdev);
2850 +err_v4l2_unregister:
2851 + v4l2_device_unregister(&unicam->v4l2_dev);
2852 +err_unicam_put:
2853 + unicam_put(unicam);
2854 +
2855 + return ret;
2856 +}
2857 +
2858 +static int unicam_remove(struct platform_device *pdev)
2859 +{
2860 + struct unicam_device *unicam = platform_get_drvdata(pdev);
2861 +
2862 + unicam_dbg(2, unicam, "%s\n", __func__);
2863 +
2864 + v4l2_async_notifier_unregister(&unicam->notifier);
2865 + v4l2_device_unregister(&unicam->v4l2_dev);
2866 + media_device_unregister(&unicam->mdev);
2867 + unregister_nodes(unicam);
2868 +
2869 + pm_runtime_disable(&pdev->dev);
2870 +
2871 + return 0;
2872 +}
2873 +
2874 +static const struct of_device_id unicam_of_match[] = {
2875 + { .compatible = "brcm,bcm2835-unicam", },
2876 + { /* sentinel */ },
2877 +};
2878 +MODULE_DEVICE_TABLE(of, unicam_of_match);
2879 +
2880 +static struct platform_driver unicam_driver = {
2881 + .probe = unicam_probe,
2882 + .remove = unicam_remove,
2883 + .driver = {
2884 + .name = UNICAM_MODULE_NAME,
2885 + .of_match_table = of_match_ptr(unicam_of_match),
2886 + },
2887 +};
2888 +
2889 +module_platform_driver(unicam_driver);
2890 +
2891 +MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com>");
2892 +MODULE_DESCRIPTION("BCM2835 Unicam driver");
2893 +MODULE_LICENSE("GPL");
2894 +MODULE_VERSION(UNICAM_VERSION);
2895 --- /dev/null
2896 +++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
2897 @@ -0,0 +1,253 @@
2898 +/* SPDX-License-Identifier: GPL-2.0-only */
2899 +
2900 +/*
2901 + * Copyright (C) 2017-2020 Raspberry Pi Trading.
2902 + * Dave Stevenson <dave.stevenson@raspberrypi.com>
2903 + */
2904 +
2905 +#ifndef VC4_REGS_UNICAM_H
2906 +#define VC4_REGS_UNICAM_H
2907 +
2908 +/*
2909 + * The following values are taken from files found within the code drop
2910 + * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
2911 + * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
2912 + * They have been modified to be only the register offset.
2913 + */
2914 +#define UNICAM_CTRL 0x000
2915 +#define UNICAM_STA 0x004
2916 +#define UNICAM_ANA 0x008
2917 +#define UNICAM_PRI 0x00c
2918 +#define UNICAM_CLK 0x010
2919 +#define UNICAM_CLT 0x014
2920 +#define UNICAM_DAT0 0x018
2921 +#define UNICAM_DAT1 0x01c
2922 +#define UNICAM_DAT2 0x020
2923 +#define UNICAM_DAT3 0x024
2924 +#define UNICAM_DLT 0x028
2925 +#define UNICAM_CMP0 0x02c
2926 +#define UNICAM_CMP1 0x030
2927 +#define UNICAM_CAP0 0x034
2928 +#define UNICAM_CAP1 0x038
2929 +#define UNICAM_ICTL 0x100
2930 +#define UNICAM_ISTA 0x104
2931 +#define UNICAM_IDI0 0x108
2932 +#define UNICAM_IPIPE 0x10c
2933 +#define UNICAM_IBSA0 0x110
2934 +#define UNICAM_IBEA0 0x114
2935 +#define UNICAM_IBLS 0x118
2936 +#define UNICAM_IBWP 0x11c
2937 +#define UNICAM_IHWIN 0x120
2938 +#define UNICAM_IHSTA 0x124
2939 +#define UNICAM_IVWIN 0x128
2940 +#define UNICAM_IVSTA 0x12c
2941 +#define UNICAM_ICC 0x130
2942 +#define UNICAM_ICS 0x134
2943 +#define UNICAM_IDC 0x138
2944 +#define UNICAM_IDPO 0x13c
2945 +#define UNICAM_IDCA 0x140
2946 +#define UNICAM_IDCD 0x144
2947 +#define UNICAM_IDS 0x148
2948 +#define UNICAM_DCS 0x200
2949 +#define UNICAM_DBSA0 0x204
2950 +#define UNICAM_DBEA0 0x208
2951 +#define UNICAM_DBWP 0x20c
2952 +#define UNICAM_DBCTL 0x300
2953 +#define UNICAM_IBSA1 0x304
2954 +#define UNICAM_IBEA1 0x308
2955 +#define UNICAM_IDI1 0x30c
2956 +#define UNICAM_DBSA1 0x310
2957 +#define UNICAM_DBEA1 0x314
2958 +#define UNICAM_MISC 0x400
2959 +
2960 +/*
2961 + * The following bitmasks are from the kernel released by Broadcom
2962 + * for Android - https://android.googlesource.com/kernel/bcm/
2963 + * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
2964 + * Unicam block as BCM2835, as defined in eg
2965 + * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
2966 + * Values reworked to use the kernel BIT and GENMASK macros.
2967 + *
2968 + * Some of the bit mnenomics have been amended to match the datasheet.
2969 + */
2970 +/* UNICAM_CTRL Register */
2971 +#define UNICAM_CPE BIT(0)
2972 +#define UNICAM_MEM BIT(1)
2973 +#define UNICAM_CPR BIT(2)
2974 +#define UNICAM_CPM_MASK GENMASK(3, 3)
2975 +#define UNICAM_CPM_CSI2 0
2976 +#define UNICAM_CPM_CCP2 1
2977 +#define UNICAM_SOE BIT(4)
2978 +#define UNICAM_DCM_MASK GENMASK(5, 5)
2979 +#define UNICAM_DCM_STROBE 0
2980 +#define UNICAM_DCM_DATA 1
2981 +#define UNICAM_SLS BIT(6)
2982 +#define UNICAM_PFT_MASK GENMASK(11, 8)
2983 +#define UNICAM_OET_MASK GENMASK(20, 12)
2984 +
2985 +/* UNICAM_STA Register */
2986 +#define UNICAM_SYN BIT(0)
2987 +#define UNICAM_CS BIT(1)
2988 +#define UNICAM_SBE BIT(2)
2989 +#define UNICAM_PBE BIT(3)
2990 +#define UNICAM_HOE BIT(4)
2991 +#define UNICAM_PLE BIT(5)
2992 +#define UNICAM_SSC BIT(6)
2993 +#define UNICAM_CRCE BIT(7)
2994 +#define UNICAM_OES BIT(8)
2995 +#define UNICAM_IFO BIT(9)
2996 +#define UNICAM_OFO BIT(10)
2997 +#define UNICAM_BFO BIT(11)
2998 +#define UNICAM_DL BIT(12)
2999 +#define UNICAM_PS BIT(13)
3000 +#define UNICAM_IS BIT(14)
3001 +#define UNICAM_PI0 BIT(15)
3002 +#define UNICAM_PI1 BIT(16)
3003 +#define UNICAM_FSI_S BIT(17)
3004 +#define UNICAM_FEI_S BIT(18)
3005 +#define UNICAM_LCI_S BIT(19)
3006 +#define UNICAM_BUF0_RDY BIT(20)
3007 +#define UNICAM_BUF0_NO BIT(21)
3008 +#define UNICAM_BUF1_RDY BIT(22)
3009 +#define UNICAM_BUF1_NO BIT(23)
3010 +#define UNICAM_DI BIT(24)
3011 +
3012 +#define UNICAM_STA_MASK_ALL \
3013 + (UNICAM_DL + \
3014 + UNICAM_SBE + \
3015 + UNICAM_PBE + \
3016 + UNICAM_HOE + \
3017 + UNICAM_PLE + \
3018 + UNICAM_SSC + \
3019 + UNICAM_CRCE + \
3020 + UNICAM_IFO + \
3021 + UNICAM_OFO + \
3022 + UNICAM_PS + \
3023 + UNICAM_PI0 + \
3024 + UNICAM_PI1)
3025 +
3026 +/* UNICAM_ANA Register */
3027 +#define UNICAM_APD BIT(0)
3028 +#define UNICAM_BPD BIT(1)
3029 +#define UNICAM_AR BIT(2)
3030 +#define UNICAM_DDL BIT(3)
3031 +#define UNICAM_CTATADJ_MASK GENMASK(7, 4)
3032 +#define UNICAM_PTATADJ_MASK GENMASK(11, 8)
3033 +
3034 +/* UNICAM_PRI Register */
3035 +#define UNICAM_PE BIT(0)
3036 +#define UNICAM_PT_MASK GENMASK(2, 1)
3037 +#define UNICAM_NP_MASK GENMASK(7, 4)
3038 +#define UNICAM_PP_MASK GENMASK(11, 8)
3039 +#define UNICAM_BS_MASK GENMASK(15, 12)
3040 +#define UNICAM_BL_MASK GENMASK(17, 16)
3041 +
3042 +/* UNICAM_CLK Register */
3043 +#define UNICAM_CLE BIT(0)
3044 +#define UNICAM_CLPD BIT(1)
3045 +#define UNICAM_CLLPE BIT(2)
3046 +#define UNICAM_CLHSE BIT(3)
3047 +#define UNICAM_CLTRE BIT(4)
3048 +#define UNICAM_CLAC_MASK GENMASK(8, 5)
3049 +#define UNICAM_CLSTE BIT(29)
3050 +
3051 +/* UNICAM_CLT Register */
3052 +#define UNICAM_CLT1_MASK GENMASK(7, 0)
3053 +#define UNICAM_CLT2_MASK GENMASK(15, 8)
3054 +
3055 +/* UNICAM_DATn Registers */
3056 +#define UNICAM_DLE BIT(0)
3057 +#define UNICAM_DLPD BIT(1)
3058 +#define UNICAM_DLLPE BIT(2)
3059 +#define UNICAM_DLHSE BIT(3)
3060 +#define UNICAM_DLTRE BIT(4)
3061 +#define UNICAM_DLSM BIT(5)
3062 +#define UNICAM_DLFO BIT(28)
3063 +#define UNICAM_DLSTE BIT(29)
3064 +
3065 +#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
3066 +
3067 +/* UNICAM_DLT Register */
3068 +#define UNICAM_DLT1_MASK GENMASK(7, 0)
3069 +#define UNICAM_DLT2_MASK GENMASK(15, 8)
3070 +#define UNICAM_DLT3_MASK GENMASK(23, 16)
3071 +
3072 +/* UNICAM_ICTL Register */
3073 +#define UNICAM_FSIE BIT(0)
3074 +#define UNICAM_FEIE BIT(1)
3075 +#define UNICAM_IBOB BIT(2)
3076 +#define UNICAM_FCM BIT(3)
3077 +#define UNICAM_TFC BIT(4)
3078 +#define UNICAM_LIP_MASK GENMASK(6, 5)
3079 +#define UNICAM_LCIE_MASK GENMASK(28, 16)
3080 +
3081 +/* UNICAM_IDI0/1 Register */
3082 +#define UNICAM_ID0_MASK GENMASK(7, 0)
3083 +#define UNICAM_ID1_MASK GENMASK(15, 8)
3084 +#define UNICAM_ID2_MASK GENMASK(23, 16)
3085 +#define UNICAM_ID3_MASK GENMASK(31, 24)
3086 +
3087 +/* UNICAM_ISTA Register */
3088 +#define UNICAM_FSI BIT(0)
3089 +#define UNICAM_FEI BIT(1)
3090 +#define UNICAM_LCI BIT(2)
3091 +
3092 +#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
3093 +
3094 +/* UNICAM_IPIPE Register */
3095 +#define UNICAM_PUM_MASK GENMASK(2, 0)
3096 + /* Unpacking modes */
3097 + #define UNICAM_PUM_NONE 0
3098 + #define UNICAM_PUM_UNPACK6 1
3099 + #define UNICAM_PUM_UNPACK7 2
3100 + #define UNICAM_PUM_UNPACK8 3
3101 + #define UNICAM_PUM_UNPACK10 4
3102 + #define UNICAM_PUM_UNPACK12 5
3103 + #define UNICAM_PUM_UNPACK14 6
3104 + #define UNICAM_PUM_UNPACK16 7
3105 +#define UNICAM_DDM_MASK GENMASK(6, 3)
3106 +#define UNICAM_PPM_MASK GENMASK(9, 7)
3107 + /* Packing modes */
3108 + #define UNICAM_PPM_NONE 0
3109 + #define UNICAM_PPM_PACK8 1
3110 + #define UNICAM_PPM_PACK10 2
3111 + #define UNICAM_PPM_PACK12 3
3112 + #define UNICAM_PPM_PACK14 4
3113 + #define UNICAM_PPM_PACK16 5
3114 +#define UNICAM_DEM_MASK GENMASK(11, 10)
3115 +#define UNICAM_DEBL_MASK GENMASK(14, 12)
3116 +#define UNICAM_ICM_MASK GENMASK(16, 15)
3117 +#define UNICAM_IDM_MASK GENMASK(17, 17)
3118 +
3119 +/* UNICAM_ICC Register */
3120 +#define UNICAM_ICFL_MASK GENMASK(4, 0)
3121 +#define UNICAM_ICFH_MASK GENMASK(9, 5)
3122 +#define UNICAM_ICST_MASK GENMASK(12, 10)
3123 +#define UNICAM_ICLT_MASK GENMASK(15, 13)
3124 +#define UNICAM_ICLL_MASK GENMASK(31, 16)
3125 +
3126 +/* UNICAM_DCS Register */
3127 +#define UNICAM_DIE BIT(0)
3128 +#define UNICAM_DIM BIT(1)
3129 +#define UNICAM_DBOB BIT(3)
3130 +#define UNICAM_FDE BIT(4)
3131 +#define UNICAM_LDP BIT(5)
3132 +#define UNICAM_EDL_MASK GENMASK(15, 8)
3133 +
3134 +/* UNICAM_DBCTL Register */
3135 +#define UNICAM_DBEN BIT(0)
3136 +#define UNICAM_BUF0_IE BIT(1)
3137 +#define UNICAM_BUF1_IE BIT(2)
3138 +
3139 +/* UNICAM_CMP[0,1] register */
3140 +#define UNICAM_PCE BIT(31)
3141 +#define UNICAM_GI BIT(9)
3142 +#define UNICAM_CPH BIT(8)
3143 +#define UNICAM_PCVC_MASK GENMASK(7, 6)
3144 +#define UNICAM_PCDT_MASK GENMASK(5, 0)
3145 +
3146 +/* UNICAM_MISC register */
3147 +#define UNICAM_FL0 BIT(6)
3148 +#define UNICAM_FL1 BIT(9)
3149 +
3150 +#endif
Staging tree of Alvaro Fernandez Rojas