git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 5f1673ff67d5e8acf590fb5a4cc2d0d5d4115927 Mon Sep 17 00:00:00 2001
   2 From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
   3 Date: Tue, 6 Nov 2018 10:14:57 +0800
   4 Subject: [PATCH] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
   5
   6 When LX2 PCIe controller is sending multiple split completions and
   7 ACK latency expires indicating that ACK should be send at priority.
   8 But because of large number of split completions and FC update DLLP,
   9 the controller does not give priority to ACK transmission. This
  10 results into ACK latency timer timeout error at the link partner and
  11 the pending TLPs are replayed by the link partner again.
  12
  13 Workaround:
  14 1. Reduce the ACK latency timeout value to a very small value.
  15 2. Restrict the number of completions from the LX2 PCIe controller
  16    to 1, by changing the Max Read Request Size (MRRS) of link partner
  17    to the same value as Max Packet size (MPS).
  18
  19 This patch implemented part 1, the part 2 can be set by kernel parameter
  20 'pci=pcie_bus_perf'
  21
  22 This ERRATA is only for LX2160A Rev1.0, and it will be fixed
  23 in Rev2.0.
  24
  25 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  26 ---
  27  drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c | 15 +++++++++++++++
  28  drivers/pci/controller/mobiveil/pcie-mobiveil.h        |  4 ++++
  29  2 files changed, 19 insertions(+)
  30
  31 --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
  32 +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
  33 @@ -80,12 +80,27 @@ static bool ls_pcie_g4_is_bridge(struct
  34         return header_type == PCI_HEADER_TYPE_BRIDGE;
  35  }
  36
  37 +static void workaround_A011451(struct ls_pcie_g4 *pcie)
  38 +{
  39 +       struct mobiveil_pcie *mv_pci = &pcie->pci;
  40 +       u32 val;
  41 +
  42 +       /* Set ACK latency timeout */
  43 +       val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
  44 +       val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
  45 +       val |= (4 << ACK_LAT_TO_VAL_SHIFT);
  46 +       csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
  47 +}
  48 +
  49  static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
  50  {
  51         struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
  52
  53         pcie->rev = csr_readb(pci, PCI_REVISION_ID);
  54
  55 +       if (pcie->rev == REV_1_0)
  56 +               workaround_A011451(pcie);
  57 +
  58         return 0;
  59  }
  60
  61 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  62 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
  63 @@ -86,6 +86,10 @@
  64  #define PAB_AXI_AMAP_PEX_WIN_H(win)    PAB_REG_ADDR(0x0bac, win)
  65  #define PAB_INTP_AXI_PIO_CLASS         0x474
  66
  67 +#define GPEX_ACK_REPLAY_TO             0x438
  68 +#define  ACK_LAT_TO_VAL_MASK           0x1fff
  69 +#define  ACK_LAT_TO_VAL_SHIFT          0
  70 +
  71  #define PAB_PEX_AMAP_CTRL(win)         PAB_REG_ADDR(0x4ba0, win)
  72  #define  AMAP_CTRL_EN_SHIFT            0
  73  #define  AMAP_CTRL_TYPE_SHIFT          1