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1 From 865433df5d11aef7cfe5d51b362b6276bddb7a15 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Fri, 2 Aug 2019 17:45:56 +0800
4 Subject: [PATCH] i2c: imx: support slave mode for imx I2C driver
5
6 The patch supports slave mode for imx I2C driver
7
8 Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 ---
11 drivers/i2c/busses/i2c-imx.c | 219 +++++++++++++++++++++++++++++++++++++++----
12 1 file changed, 201 insertions(+), 18 deletions(-)
13
14 --- a/drivers/i2c/busses/i2c-imx.c
15 +++ b/drivers/i2c/busses/i2c-imx.c
16 @@ -265,6 +265,9 @@ struct imx_i2c_struct {
17 int pmuxcr_set;
18 int pmuxcr_endian;
19 void __iomem *pmuxcr_addr;
20 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
21 + struct i2c_client *slave;
22 +#endif
23 };
24
25 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
26 @@ -357,6 +360,14 @@ static inline unsigned char imx_i2c_read
27 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
28 }
29
30 +/* Set up i2c controller register and i2c status register to default value. */
31 +static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
32 +{
33 + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
34 + i2c_imx, IMX_I2C_I2CR);
35 + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
36 +}
37 +
38 /* Functions for DMA support */
39 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
40 dma_addr_t phy_addr)
41 @@ -705,21 +716,33 @@ static void i2c_imx_stop(struct imx_i2c_
42 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
43 }
44
45 -static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
46 +/* Clear interrupt flag bit */
47 +static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
48 {
49 - struct imx_i2c_struct *i2c_imx = dev_id;
50 - unsigned int temp;
51 + status &= ~I2SR_IIF;
52 + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
53 + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
54 +}
55
56 - temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
57 - if (temp & I2SR_IIF) {
58 - /* save status register */
59 - i2c_imx->i2csr = temp;
60 - i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
61 - wake_up(&i2c_imx->queue);
62 - return IRQ_HANDLED;
63 - }
64 +/* Clear arbitration lost bit */
65 +static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct *i2c_imx)
66 +{
67 + status &= ~I2SR_IAL;
68 + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
69 + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR);
70 +}
71 +
72 +static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
73 +{
74 + unsigned int status;
75 +
76 + /* Save status register */
77 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
78 + i2c_imx->i2csr = status | I2SR_IIF;
79 +
80 + wake_up(&i2c_imx->queue);
81
82 - return IRQ_NONE;
83 + return IRQ_HANDLED;
84 }
85
86 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
87 @@ -1094,6 +1117,13 @@ static int i2c_imx_xfer(struct i2c_adapt
88
89 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
90
91 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
92 + if (i2c_imx->slave) {
93 + dev_err(&i2c_imx->adapter.dev, "Please not do operations of master mode in slave mode");
94 + return -EBUSY;
95 + }
96 +#endif
97 +
98 if (!pm_runtime_enabled(i2c_imx->adapter.dev.parent)) {
99 pm_runtime_enable(i2c_imx->adapter.dev.parent);
100 enable_runtime_pm = true;
101 @@ -1307,11 +1337,169 @@ static u32 i2c_imx_func(struct i2c_adapt
102 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
103 }
104
105 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
106 +static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
107 +{
108 + int temp;
109 +
110 + /* Resume */
111 + temp = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
112 + if (temp < 0) {
113 + dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
114 + return temp;
115 + }
116 +
117 + /* Set slave addr. */
118 + imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
119 +
120 + i2c_imx_reset_regs(i2c_imx);
121 +
122 + /* Enable module */
123 + temp = i2c_imx->hwdata->i2cr_ien_opcode;
124 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
125 +
126 + /* Enable interrupt from i2c module */
127 + temp |= I2CR_IIEN;
128 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
129 +
130 + /* Wait controller to be stable */
131 + usleep_range(50, 150);
132 + return 0;
133 +}
134 +
135 +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx)
136 +{
137 + unsigned int status, ctl;
138 + u8 value;
139 +
140 + if (!i2c_imx->slave) {
141 + dev_err(&i2c_imx->adapter.dev, "cannot deal with slave irq,i2c_imx->slave is null");
142 + return IRQ_NONE;
143 + }
144 +
145 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
146 + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
147 + if (status & I2SR_IAL) { /* Arbitration lost */
148 + i2c_imx_clr_al_bit(status, i2c_imx);
149 + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
150 + if (status & I2SR_SRW) { /* Master wants to read from us*/
151 + dev_dbg(&i2c_imx->adapter.dev, "read requested");
152 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value);
153 +
154 + /* Slave transmit */
155 + ctl |= I2CR_MTX;
156 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
157 +
158 + /* Send data */
159 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
160 + } else { /* Master wants to write to us */
161 + dev_dbg(&i2c_imx->adapter.dev, "write requested");
162 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
163 +
164 + /* Slave receive */
165 + ctl &= ~I2CR_MTX;
166 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
167 + /* Dummy read */
168 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
169 + }
170 + } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
171 + if (status & I2SR_IBB) { /* No STOP signal detected */
172 + ctl &= ~I2CR_MTX;
173 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
174 +
175 + value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
176 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
177 + } else { /* STOP signal is detected */
178 + dev_dbg(&i2c_imx->adapter.dev,
179 + "STOP signal detected");
180 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value);
181 + }
182 + } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
183 + ctl |= I2CR_MTX;
184 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
185 +
186 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value);
187 +
188 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
189 + } else { /* Transmit mode received NAK */
190 + ctl &= ~I2CR_MTX;
191 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
192 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
193 + }
194 + return IRQ_HANDLED;
195 +}
196 +
197 +static int i2c_imx_reg_slave(struct i2c_client *client)
198 +{
199 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
200 + int ret;
201 + if (i2c_imx->slave)
202 + return -EBUSY;
203 +
204 + i2c_imx->slave = client;
205 +
206 + ret = i2c_imx_slave_init(i2c_imx);
207 + if (ret < 0)
208 + dev_err(&i2c_imx->adapter.dev, "failed to switch to slave mode");
209 +
210 + return ret;
211 +}
212 +
213 +static int i2c_imx_unreg_slave(struct i2c_client *client)
214 +{
215 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
216 + int ret;
217 +
218 + if (!i2c_imx->slave)
219 + return -EINVAL;
220 +
221 + /* Reset slave address. */
222 + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
223 +
224 + i2c_imx_reset_regs(i2c_imx);
225 +
226 + i2c_imx->slave = NULL;
227 +
228 + /* Suspend */
229 + ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
230 + if (ret < 0)
231 + dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
232 +
233 + return ret;
234 +}
235 +#endif
236 +
237 static const struct i2c_algorithm i2c_imx_algo = {
238 .master_xfer = i2c_imx_xfer,
239 .functionality = i2c_imx_func,
240 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
241 + .reg_slave = i2c_imx_reg_slave,
242 + .unreg_slave = i2c_imx_unreg_slave,
243 +#endif
244 };
245
246 +static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
247 +{
248 + struct imx_i2c_struct *i2c_imx = dev_id;
249 + unsigned int status, ctl;
250 + irqreturn_t irq_status = IRQ_NONE;
251 +
252 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
253 + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
254 +
255 + if (status & I2SR_IIF) {
256 + i2c_imx_clr_if_bit(status, i2c_imx);
257 + if (ctl & I2CR_MSTA)
258 + irq_status = i2c_imx_master_isr(i2c_imx);
259 +#if IS_ENABLED(CONFIG_I2C_SLAVE)
260 + else
261 + irq_status = i2c_imx_slave_isr(i2c_imx);
262 +#endif
263 + }
264 +
265 + return irq_status;
266 +}
267 +
268 static int i2c_imx_probe(struct platform_device *pdev)
269 {
270 struct imx_i2c_struct *i2c_imx;
271 @@ -1420,10 +1608,7 @@ static int i2c_imx_probe(struct platform
272 if (is_imx7d_i2c(i2c_imx) && i2c_imx->bitrate > IMX_I2C_MAX_E_BIT_RATE)
273 i2c_imx->bitrate = IMX_I2C_MAX_E_BIT_RATE;
274
275 - /* Set up chip registers to defaults */
276 - imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
277 - i2c_imx, IMX_I2C_I2CR);
278 - imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
279 + i2c_imx_reset_regs(i2c_imx);
280
281 /* Init optional bus recovery */
282 if (of_match_node(pinmux_of_match, pdev->dev.of_node))
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