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1 From 1882af9f2c7533c6cd2dea5811b4e69f9a151f29 Mon Sep 17 00:00:00 2001
2 From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
3 Date: Fri, 24 Jun 2016 10:45:39 +0530
4 Subject: [PATCH 63/93] board: freescale: ls1012a: Enable secure DDR on
5 LS1012A platforms
6
7 PPA binary needs to be relocated on secure DDR, hence marking out
8 a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
9 is set
10
11 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
12 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
13 ---
14 arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
15 board/freescale/ls1012afrdm/ls1012afrdm.c | 28 +++++++++++++++++++++
16 board/freescale/ls1012aqds/ls1012aqds.c | 28 +++++++++++++++++++++
17 board/freescale/ls1012ardb/ls1012ardb.c | 28 +++++++++++++++++++++
18 include/configs/ls1012a_common.h | 1 +
19 5 files changed, 88 insertions(+)
20
21 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
22 index 679be6c..efaa79a 100644
23 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
24 +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
25 @@ -222,6 +222,9 @@
26 #define GICD_BASE 0x01401000
27 #define GICC_BASE 0x01402000
28
29 +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
30 +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
31 +
32 #define CONFIG_SYS_FSL_CCSR_GUR_BE
33 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
34 #define CONFIG_SYS_FSL_ESDHC_BE
35 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
36 index 6856250..c691a76 100644
37 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c
38 +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
39 @@ -176,3 +176,31 @@ int ft_board_setup(void *blob, bd_t *bd)
40
41 return 0;
42 }
43 +
44 +void dram_init_banksize(void)
45 +{
46 + /*
47 + * gd->secure_ram tracks the location of secure memory.
48 + * It was set as if the memory starts from 0.
49 + * The address needs to add the offset of its bank.
50 + */
51 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
52 + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
53 + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
54 + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
55 + gd->bd->bi_dram[1].size = gd->ram_size -
56 + CONFIG_SYS_DDR_BLOCK1_SIZE;
57 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
58 + gd->secure_ram = gd->bd->bi_dram[1].start +
59 + gd->secure_ram -
60 + CONFIG_SYS_DDR_BLOCK1_SIZE;
61 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
62 +#endif
63 + } else {
64 + gd->bd->bi_dram[0].size = gd->ram_size;
65 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
66 + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
67 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
68 +#endif
69 + }
70 +}
71 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
72 index 56004ea..516f0c3 100644
73 --- a/board/freescale/ls1012aqds/ls1012aqds.c
74 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
75 @@ -240,3 +240,31 @@ int ft_board_setup(void *blob, bd_t *bd)
76 return 0;
77 }
78 #endif
79 +
80 +void dram_init_banksize(void)
81 +{
82 + /*
83 + * gd->secure_ram tracks the location of secure memory.
84 + * It was set as if the memory starts from 0.
85 + * The address needs to add the offset of its bank.
86 + */
87 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
88 + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
89 + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
90 + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
91 + gd->bd->bi_dram[1].size = gd->ram_size -
92 + CONFIG_SYS_DDR_BLOCK1_SIZE;
93 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
94 + gd->secure_ram = gd->bd->bi_dram[1].start +
95 + gd->secure_ram -
96 + CONFIG_SYS_DDR_BLOCK1_SIZE;
97 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
98 +#endif
99 + } else {
100 + gd->bd->bi_dram[0].size = gd->ram_size;
101 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
102 + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
103 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
104 +#endif
105 + }
106 +}
107 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
108 index ad4d8ee..8340f14 100644
109 --- a/board/freescale/ls1012ardb/ls1012ardb.c
110 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
111 @@ -235,3 +235,31 @@ int ft_board_setup(void *blob, bd_t *bd)
112
113 return 0;
114 }
115 +
116 +void dram_init_banksize(void)
117 +{
118 + /*
119 + * gd->secure_ram tracks the location of secure memory.
120 + * It was set as if the memory starts from 0.
121 + * The address needs to add the offset of its bank.
122 + */
123 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
124 + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
125 + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
126 + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
127 + gd->bd->bi_dram[1].size = gd->ram_size -
128 + CONFIG_SYS_DDR_BLOCK1_SIZE;
129 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
130 + gd->secure_ram = gd->bd->bi_dram[1].start +
131 + gd->secure_ram -
132 + CONFIG_SYS_DDR_BLOCK1_SIZE;
133 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
134 +#endif
135 + } else {
136 + gd->bd->bi_dram[0].size = gd->ram_size;
137 +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
138 + gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
139 + gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
140 +#endif
141 + }
142 +}
143 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
144 index 7c0e64f..4c7c697 100644
145 --- a/include/configs/ls1012a_common.h
146 +++ b/include/configs/ls1012a_common.h
147 @@ -36,6 +36,7 @@
148 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
149 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
150 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
151 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
152
153 /* Generic Timer Definitions */
154 #define COUNTER_FREQUENCY 25000000 /* 12MHz */
155 --
156 1.7.9.5
157
Staging tree of Matthias Schiffer