52af732c4450f9f2ca08b2d5310d4102ddcd8aa5
[openwrt/staging/mkresin.git] /
1 From 3fe0073d116d9902df08761c1cf0d733dd4c38fc Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
3 Date: Wed, 8 Dec 2021 06:03:50 +0100
4 Subject: [PATCH] PCI: aardvark: Optimize writing PCI_EXP_RTCTL_PMEIE and
5 PCI_EXP_RTSTA_PME on emulated bridge
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 To optimize advk_pci_bridge_emul_pcie_conf_write() code, touch
11 PCIE_ISR0_REG and PCIE_ISR0_MASK_REG registers only when it is really
12 needed, when processing PCI_EXP_RTCTL_PMEIE and PCI_EXP_RTSTA_PME bits.
13
14 Signed-off-by: Pali Rohár <pali@kernel.org>
15 Signed-off-by: Marek Behún <kabel@kernel.org>
16 ---
17 drivers/pci/controller/pci-aardvark.c | 20 +++++++++++---------
18 1 file changed, 11 insertions(+), 9 deletions(-)
19
20 diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
21 index 44d9c8c4d258..efd7e53b5e06 100644
22 --- a/drivers/pci/controller/pci-aardvark.c
23 +++ b/drivers/pci/controller/pci-aardvark.c
24 @@ -933,19 +933,21 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
25 advk_pcie_wait_for_retrain(pcie);
26 break;
27
28 - case PCI_EXP_RTCTL: {
29 + case PCI_EXP_RTCTL:
30 /* Only mask/unmask PME interrupt */
31 - u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
32 - ~PCIE_MSG_PM_PME_MASK;
33 - if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
34 - val |= PCIE_MSG_PM_PME_MASK;
35 - advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
36 + if (mask & PCI_EXP_RTCTL_PMEIE) {
37 + u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
38 + if (new & PCI_EXP_RTCTL_PMEIE)
39 + val &= ~PCIE_MSG_PM_PME_MASK;
40 + else
41 + val |= PCIE_MSG_PM_PME_MASK;
42 + advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
43 + }
44 break;
45 - }
46
47 case PCI_EXP_RTSTA:
48 - new = (new & PCI_EXP_RTSTA_PME) >> 9;
49 - advk_writel(pcie, new, PCIE_ISR0_REG);
50 + if (new & PCI_EXP_RTSTA_PME)
51 + advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
52 break;
53
54 case PCI_EXP_DEVCTL:
55 --
56 2.34.1
57