git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 0b0d606eb9650fa01dd5621e072aa29a10544399 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Tue, 22 Aug 2023 17:33:12 +0100
   4 Subject: [PATCH 113/250] net: ethernet: mtk_eth_soc: support 36-bit DMA
   5  addressing on MT7988
   6
   7 Systems having 4 GiB of RAM and more require DMA addressing beyond the
   8 current 32-bit limit. Starting from MT7988 the hardware now supports
   9 36-bit DMA addressing, let's use that new capability in the driver to
  10 avoid running into swiotlb on systems with 4 GiB of RAM or more.
  11
  12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  13 Link: https://lore.kernel.org/r/95b919c98876c9e49761e44662e7c937479eecb8.1692721443.git.daniel@makrotopia.org
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++++++++++++++--
  17  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 22 +++++++++++++--
  18  2 files changed, 48 insertions(+), 4 deletions(-)
  19
  20 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  22 @@ -1265,6 +1265,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  23         data = TX_DMA_PLEN0(info->size);
  24         if (info->last)
  25                 data |= TX_DMA_LS0;
  26 +
  27 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
  28 +               data |= TX_DMA_PREP_ADDR64(info->addr);
  29 +
  30         WRITE_ONCE(desc->txd3, data);
  31
  32          /* set forward port */
  33 @@ -1932,6 +1936,7 @@ static int mtk_poll_rx(struct napi_struc
  34         bool xdp_flush = false;
  35         int idx;
  36         struct sk_buff *skb;
  37 +       u64 addr64 = 0;
  38         u8 *data, *new_data;
  39         struct mtk_rx_dma_v2 *rxd, trxd;
  40         int done = 0, bytes = 0;
  41 @@ -2047,7 +2052,10 @@ static int mtk_poll_rx(struct napi_struc
  42                                 goto release_desc;
  43                         }
  44
  45 -                       dma_unmap_single(eth->dma_dev, trxd.rxd1,
  46 +                       if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
  47 +                               addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
  48 +
  49 +                       dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
  50                                          ring->buf_size, DMA_FROM_DEVICE);
  51
  52                         skb = build_skb(data, ring->frag_size);
  53 @@ -2113,6 +2121,9 @@ release_desc:
  54                 else
  55                         rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  56
  57 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
  58 +                       rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
  59 +
  60                 ring->calc_idx = idx;
  61                 done++;
  62         }
  63 @@ -2597,6 +2608,9 @@ static int mtk_rx_alloc(struct mtk_eth *
  64                 else
  65                         rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  66
  67 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
  68 +                       rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
  69 +
  70                 rxd->rxd3 = 0;
  71                 rxd->rxd4 = 0;
  72                 if (mtk_is_netsys_v2_or_greater(eth)) {
  73 @@ -2643,6 +2657,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  74
  75  static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
  76  {
  77 +       u64 addr64 = 0;
  78         int i;
  79
  80         if (ring->data && ring->dma) {
  81 @@ -2656,7 +2671,10 @@ static void mtk_rx_clean(struct mtk_eth
  82                         if (!rxd->rxd1)
  83                                 continue;
  84
  85 -                       dma_unmap_single(eth->dma_dev, rxd->rxd1,
  86 +                       if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
  87 +                               addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
  88 +
  89 +                       dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
  90                                          ring->buf_size, DMA_FROM_DEVICE);
  91                         mtk_rx_put_buff(ring, ring->data[i], false);
  92                 }
  93 @@ -4645,6 +4663,14 @@ static int mtk_probe(struct platform_dev
  94                 }
  95         }
  96
  97 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
  98 +               err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
  99 +               if (err) {
 100 +                       dev_err(&pdev->dev, "Wrong DMA config\n");
 101 +                       return -EINVAL;
 102 +               }
 103 +       }
 104 +
 105         spin_lock_init(&eth->page_lock);
 106         spin_lock_init(&eth->tx_irq_lock);
 107         spin_lock_init(&eth->rx_irq_lock);
 108 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 109 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 110 @@ -331,6 +331,14 @@
 111  #define TX_DMA_PLEN1(x)                ((x) & eth->soc->txrx.dma_max_len)
 112  #define TX_DMA_SWC             BIT(14)
 113  #define TX_DMA_PQID            GENMASK(3, 0)
 114 +#define TX_DMA_ADDR64_MASK     GENMASK(3, 0)
 115 +#if IS_ENABLED(CONFIG_64BIT)
 116 +# define TX_DMA_GET_ADDR64(x)  (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
 117 +# define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
 118 +#else
 119 +# define TX_DMA_GET_ADDR64(x)  (0)
 120 +# define TX_DMA_PREP_ADDR64(x) (0)
 121 +#endif
 122
 123  /* PDMA on MT7628 */
 124  #define TX_DMA_DONE            BIT(31)
 125 @@ -343,6 +351,14 @@
 126  #define RX_DMA_PREP_PLEN0(x)   (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
 127  #define RX_DMA_GET_PLEN0(x)    (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
 128  #define RX_DMA_VTAG            BIT(15)
 129 +#define RX_DMA_ADDR64_MASK     GENMASK(3, 0)
 130 +#if IS_ENABLED(CONFIG_64BIT)
 131 +# define RX_DMA_GET_ADDR64(x)  (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
 132 +# define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
 133 +#else
 134 +# define RX_DMA_GET_ADDR64(x)  (0)
 135 +# define RX_DMA_PREP_ADDR64(x) (0)
 136 +#endif
 137
 138  /* QDMA descriptor rxd3 */
 139  #define RX_DMA_VID(x)          ((x) & VLAN_VID_MASK)
 140 @@ -939,6 +955,7 @@ enum mkt_eth_capabilities {
 141         MTK_RSTCTRL_PPE2_BIT,
 142         MTK_U3_COPHY_V2_BIT,
 143         MTK_SRAM_BIT,
 144 +       MTK_36BIT_DMA_BIT,
 145
 146         /* MUX BITS*/
 147         MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
 148 @@ -975,6 +992,7 @@ enum mkt_eth_capabilities {
 149  #define MTK_RSTCTRL_PPE2       BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
 150  #define MTK_U3_COPHY_V2                BIT_ULL(MTK_U3_COPHY_V2_BIT)
 151  #define MTK_SRAM               BIT_ULL(MTK_SRAM_BIT)
 152 +#define MTK_36BIT_DMA  BIT_ULL(MTK_36BIT_DMA_BIT)
 153
 154  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW          \
 155         BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
 156 @@ -1056,8 +1074,8 @@ enum mkt_eth_capabilities {
 157                       MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
 158                       MTK_RSTCTRL_PPE1 | MTK_SRAM)
 159
 160 -#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
 161 -                     MTK_RSTCTRL_PPE2 | MTK_SRAM)
 162 +#define MT7988_CAPS  (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
 163 +                     MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
 164
 165  struct mtk_tx_dma_desc_info {
 166         dma_addr_t      addr;