5214e842c82656eb59b843a0fb9040cad785674e
[openwrt/staging/jow.git] /
1 From c44f6ac1a31961b0d4faf982ee42167de5ac1672 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 19 Jul 2023 17:17:03 +0800
4 Subject: [PATCH 18/29] net: mediatek: fix direct MDIO clause 45 access via SoC
5
6 The original direct MDIO clause 45 access via SoC is missing the
7 data output. This patch adds it back to ensure MDIO clause 45 can
8 work properly for external PHYs.
9
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/net/mtk_eth.c | 4 ++--
13 1 file changed, 2 insertions(+), 2 deletions(-)
14
15 --- a/drivers/net/mtk_eth.c
16 +++ b/drivers/net/mtk_eth.c
17 @@ -198,7 +198,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
18 (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
19 (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
20
21 - if (cmd == MDIO_CMD_WRITE)
22 + if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
23 val |= data & MDIO_RW_DATA_M;
24
25 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
26 @@ -210,7 +210,7 @@ static int mtk_mii_rw(struct mtk_eth_pri
27 return ret;
28 }
29
30 - if (cmd == MDIO_CMD_READ) {
31 + if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
32 val = mtk_gmac_read(priv, GMAC_PIAC_REG);
33 return val & MDIO_RW_DATA_M;
34 }