git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 27 Jul 2023 09:07:28 +0200
   4 Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw
   5  flowtable_offload for MT7988 SoC
   6
   7 Enable hw Packet Process Engine (PPE) for MT7988 SoC.
   8
   9 Tested-by: Daniel Golle <daniel@makrotopia.org>
  10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  11 Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/ethernet/mediatek/mtk_eth_soc.c |  3 +++
  15  drivers/net/ethernet/mediatek/mtk_ppe.c     | 19 +++++++++++++++----
  16  drivers/net/ethernet/mediatek/mtk_ppe.h     | 19 ++++++++++++++++++-
  17  3 files changed, 36 insertions(+), 5 deletions(-)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 @@ -4976,6 +4976,9 @@ static const struct mtk_soc_data mt7988_
  22         .required_clks = MT7988_CLKS_BITMAP,
  23         .required_pctl = false,
  24         .version = 3,
  25 +       .offload_version = 2,
  26 +       .hash_offset = 4,
  27 +       .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
  28         .txrx = {
  29                 .txd_size = sizeof(struct mtk_tx_dma_v2),
  30                 .rxd_size = sizeof(struct mtk_rx_dma_v2),
  31 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
  32 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
  33 @@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et
  34         struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
  35         u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
  36
  37 -       if (mtk_is_netsys_v2_or_greater(eth)) {
  38 +       switch (eth->soc->version) {
  39 +       case 3:
  40 +               *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
  41 +               *ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
  42 +                        MTK_FOE_IB2_WDMA_WINFO_V2;
  43 +               l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
  44 +                            FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
  45 +               break;
  46 +       case 2:
  47                 *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
  48                 *ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
  49                          MTK_FOE_IB2_WDMA_WINFO_V2;
  50                 l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
  51                             FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
  52 -       } else {
  53 +               break;
  54 +       default:
  55                 *ib2 &= ~MTK_FOE_IB2_PORT_MG;
  56                 *ib2 |= MTK_FOE_IB2_WDMA_WINFO;
  57                 if (wdma_idx)
  58 @@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
  59                 l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
  60                             FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
  61                             FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
  62 +               break;
  63         }
  64
  65         return 0;
  66 @@ -956,8 +966,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  67         mtk_ppe_init_foe_table(ppe);
  68         ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
  69
  70 -       val = MTK_PPE_TB_CFG_ENTRY_80B |
  71 -             MTK_PPE_TB_CFG_AGE_NON_L4 |
  72 +       val = MTK_PPE_TB_CFG_AGE_NON_L4 |
  73               MTK_PPE_TB_CFG_AGE_UNBIND |
  74               MTK_PPE_TB_CFG_AGE_TCP |
  75               MTK_PPE_TB_CFG_AGE_UDP |
  76 @@ -973,6 +982,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  77                          MTK_PPE_ENTRIES_SHIFT);
  78         if (mtk_is_netsys_v2_or_greater(ppe->eth))
  79                 val |= MTK_PPE_TB_CFG_INFO_SEL;
  80 +       if (!mtk_is_netsys_v3_or_greater(ppe->eth))
  81 +               val |= MTK_PPE_TB_CFG_ENTRY_80B;
  82         ppe_w32(ppe, MTK_PPE_TB_CFG, val);
  83
  84         ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
  85 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
  86 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
  87 @@ -85,6 +85,17 @@ enum {
  88  #define MTK_FOE_WINFO_BSS              GENMASK(5, 0)
  89  #define MTK_FOE_WINFO_WCID             GENMASK(15, 6)
  90
  91 +#define MTK_FOE_WINFO_BSS_V3           GENMASK(23, 16)
  92 +#define MTK_FOE_WINFO_WCID_V3          GENMASK(15, 0)
  93 +
  94 +#define MTK_FOE_WINFO_PAO_USR_INFO     GENMASK(15, 0)
  95 +#define MTK_FOE_WINFO_PAO_TID          GENMASK(19, 16)
  96 +#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20)
  97 +#define MTK_FOE_WINFO_PAO_IS_PRIOR     BIT(21)
  98 +#define MTK_FOE_WINFO_PAO_IS_SP                BIT(22)
  99 +#define MTK_FOE_WINFO_PAO_HF           BIT(23)
 100 +#define MTK_FOE_WINFO_PAO_AMSDU_EN     BIT(24)
 101 +
 102  enum {
 103         MTK_FOE_STATE_INVALID,
 104         MTK_FOE_STATE_UNBIND,
 105 @@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
 106         u16 pppoe_id;
 107         u16 src_mac_lo;
 108
 109 +       /* netsys_v2 */
 110         u16 minfo;
 111         u16 winfo;
 112 +
 113 +       /* netsys_v3 */
 114 +       u32 w3info;
 115 +       u32 wpao;
 116  };
 117
 118  /* software-only entry type */
 119 @@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
 120
 121  #define MTK_FOE_ENTRY_V1_SIZE  80
 122  #define MTK_FOE_ENTRY_V2_SIZE  96
 123 +#define MTK_FOE_ENTRY_V3_SIZE  128
 124
 125  struct mtk_foe_entry {
 126         u32 ib1;
 127 @@ -228,7 +245,7 @@ struct mtk_foe_entry {
 128                 struct mtk_foe_ipv4_dslite dslite;
 129                 struct mtk_foe_ipv6 ipv6;
 130                 struct mtk_foe_ipv6_6rd ipv6_6rd;
 131 -               u32 data[23];
 132 +               u32 data[31];
 133         };
 134  };
 135