git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From c0308743202449028d2b839d9b01d3d5ed2b210a Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Wed, 27 Nov 2019 19:21:13 +0200
   4 Subject: [PATCH] enetc: Set MDIO_CFG_HOLD to the recommended value of 2
   5
   6 This increases the MDIO hold time to 5 enet_clk cycles from the previous
   7 value of 0. This is actually the out-of-reset value, that the driver was
   8 previously overwriting with 0. Zero worked for the external MDIO, but
   9 breaks communication with the internal MDIO buses on which the PCS of
  10 ENETC SI's and Felix switch are found.
  11
  12 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  13 ---
  14  drivers/net/ethernet/freescale/enetc/enetc_mdio.c | 12 ++++++++----
  15  1 file changed, 8 insertions(+), 4 deletions(-)
  16
  17 --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
  18 +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
  19 @@ -31,15 +31,19 @@ static inline void _enetc_mdio_wr(struct
  20         _enetc_mdio_wr(mdio_priv, ENETC_##off, val)
  21  #define enetc_mdio_rd_reg(off) enetc_mdio_rd(mdio_priv, off)
  22
  23 -#define ENETC_MDC_DIV          258
  24 -
  25  #define MDIO_CFG_CLKDIV(x)     ((((x) >> 1) & 0xff) << 8)
  26  #define MDIO_CFG_BSY           BIT(0)
  27  #define MDIO_CFG_RD_ER         BIT(1)
  28 +#define MDIO_CFG_HOLD(x)       (((x) << 2) & GENMASK(4, 2))
  29  #define MDIO_CFG_ENC45         BIT(6)
  30   /* external MDIO only - driven on neg MDC edge */
  31  #define MDIO_CFG_NEG           BIT(23)
  32
  33 +#define ENETC_EMDIO_CFG \
  34 +       (MDIO_CFG_HOLD(2) | \
  35 +        MDIO_CFG_CLKDIV(258) | \
  36 +        MDIO_CFG_NEG)
  37 +
  38  #define MDIO_CTL_DEV_ADDR(x)   ((x) & 0x1f)
  39  #define MDIO_CTL_PORT_ADDR(x)  (((x) & 0x1f) << 5)
  40  #define MDIO_CTL_READ          BIT(15)
  41 @@ -61,7 +65,7 @@ int enetc_mdio_write(struct mii_bus *bus
  42         u16 dev_addr;
  43         int ret;
  44
  45 -       mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
  46 +       mdio_cfg = ENETC_EMDIO_CFG;
  47         if (regnum & MII_ADDR_C45) {
  48                 dev_addr = (regnum >> 16) & 0x1f;
  49                 mdio_cfg |= MDIO_CFG_ENC45;
  50 @@ -108,7 +112,7 @@ int enetc_mdio_read(struct mii_bus *bus,
  51         u16 dev_addr, value;
  52         int ret;
  53
  54 -       mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
  55 +       mdio_cfg = ENETC_EMDIO_CFG;
  56         if (regnum & MII_ADDR_C45) {
  57                 dev_addr = (regnum >> 16) & 0x1f;
  58                 mdio_cfg |= MDIO_CFG_ENC45;