git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Fri, 27 Aug 2021 11:27:52 +0200
   4 Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to
   5  2500Base-X
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather
  11 2500Base-X mode which runs at 3.125 Gbps speed.
  12
  13 Rename macro names and comments to 2500Base-X.
  14
  15 Signed-off-by: Pali Rohár <pali@kernel.org>
  16 Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++-----
  20  1 file changed, 5 insertions(+), 5 deletions(-)
  21
  22 --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
  23 +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
  24 @@ -29,7 +29,7 @@
  25
  26  #define COMPHY_FW_MODE_SATA                    0x1
  27  #define COMPHY_FW_MODE_SGMII                   0x2
  28 -#define COMPHY_FW_MODE_HS_SGMII                        0x3
  29 +#define COMPHY_FW_MODE_2500BASEX               0x3
  30  #define COMPHY_FW_MODE_USB3H                   0x4
  31  #define COMPHY_FW_MODE_USB3D                   0x5
  32  #define COMPHY_FW_MODE_PCIE                    0x6
  33 @@ -40,7 +40,7 @@
  34
  35  #define COMPHY_FW_SPEED_1_25G                  0 /* SGMII 1G */
  36  #define COMPHY_FW_SPEED_2_5G                   1
  37 -#define COMPHY_FW_SPEED_3_125G                 2 /* SGMII 2.5G */
  38 +#define COMPHY_FW_SPEED_3_125G                 2 /* 2500BASE-X */
  39  #define COMPHY_FW_SPEED_5G                     3
  40  #define COMPHY_FW_SPEED_5_15625G               4 /* XFI 5G */
  41  #define COMPHY_FW_SPEED_6G                     5
  42 @@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_c
  43         MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
  44                                     COMPHY_FW_MODE_SGMII),
  45         MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
  46 -                                   COMPHY_FW_MODE_HS_SGMII),
  47 +                                   COMPHY_FW_MODE_2500BASEX),
  48         /* lane 1 */
  49         MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
  50                                     COMPHY_FW_MODE_PCIE),
  51         MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
  52                                     COMPHY_FW_MODE_SGMII),
  53         MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
  54 -                                   COMPHY_FW_MODE_HS_SGMII),
  55 +                                   COMPHY_FW_MODE_2500BASEX),
  56         /* lane 2 */
  57         MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
  58                                     COMPHY_FW_MODE_SATA),
  59 @@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(s
  60                                                  COMPHY_FW_SPEED_1_25G);
  61                         break;
  62                 case PHY_INTERFACE_MODE_2500BASEX:
  63 -                       dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
  64 +                       dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
  65                                 lane->id);
  66                         fw_param = COMPHY_FW_NET(fw_mode, lane->port,
  67                                                  COMPHY_FW_SPEED_3_125G);