git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 5cf7797526ee81bea0f627bccaa3d887f48f53e0 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:10:47 +0100
   4 Subject: [PATCH 02/10] net: mtk_eth_soc: eliminate unnecessary error handling
   5
   6 The functions called by the pcs_config() method always return zero, so
   7 there is no point trying to handle an error from these functions. Make
   8 these functions void, eliminate the "err" variable and simply return
   9 zero from the pcs_config() function itself.
  10
  11 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  13 ---
  14  drivers/net/ethernet/mediatek/mtk_sgmii.c | 18 ++++++------------
  15  1 file changed, 6 insertions(+), 12 deletions(-)
  16
  17 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  18 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  19 @@ -20,7 +20,7 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
  20  }
  21
  22  /* For SGMII interface mode */
  23 -static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  24 +static void mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  25  {
  26         unsigned int val;
  27
  28 @@ -39,16 +39,13 @@ static int mtk_pcs_setup_mode_an(struct
  29         regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  30         val &= ~SGMII_PHYA_PWD;
  31         regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  32 -
  33 -       return 0;
  34 -
  35  }
  36
  37  /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
  38   * fixed speed.
  39   */
  40 -static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
  41 -                                   phy_interface_t interface)
  42 +static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
  43 +                                    phy_interface_t interface)
  44  {
  45         unsigned int val;
  46
  47 @@ -73,8 +70,6 @@ static int mtk_pcs_setup_mode_force(stru
  48         regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  49         val &= ~SGMII_PHYA_PWD;
  50         regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  51 -
  52 -       return 0;
  53  }
  54
  55  static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
  56 @@ -83,15 +78,14 @@ static int mtk_pcs_config(struct phylink
  57                           bool permit_pause_to_mac)
  58  {
  59         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  60 -       int err = 0;
  61
  62         /* Setup SGMIISYS with the determined property */
  63         if (interface != PHY_INTERFACE_MODE_SGMII)
  64 -               err = mtk_pcs_setup_mode_force(mpcs, interface);
  65 +               mtk_pcs_setup_mode_force(mpcs, interface);
  66         else if (phylink_autoneg_inband(mode))
  67 -               err = mtk_pcs_setup_mode_an(mpcs);
  68 +               mtk_pcs_setup_mode_an(mpcs);
  69
  70 -       return err;
  71 +       return 0;
  72  }
  73
  74  static void mtk_pcs_restart_an(struct phylink_pcs *pcs)