projects / openwrt / staging / jogo.git / blob
? search:


4c84703cd94c077ea87954dda9171c70fb60ac95
[openwrt/staging/jogo.git] /
1 From 901f3fbe13c3e56f0742e02717ccbfabbc95c463 Mon Sep 17 00:00:00 2001
2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
3 Date: Wed, 18 May 2022 15:55:22 +0100
4 Subject: [PATCH 11/12] net: mtk_eth_soc: convert code structure to suit split
5 PCS support
6
7 Provide a mtk_pcs structure which encapsulates everything that the PCS
8 functions need (the regmap and ana_rgc3 offset), and use this in the
9 PCS functions. Provide shim functions to convert from the existing
10 "mtk_sgmii_*" interface to the converted PCS functions.
11
12 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
14 ---
15 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 15 ++-
16 drivers/net/ethernet/mediatek/mtk_sgmii.c | 123 +++++++++++---------
17 2 files changed, 79 insertions(+), 59 deletions(-)
18
19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
21 @@ -959,16 +959,23 @@ struct mtk_soc_data {
22 /* currently no SoC has more than 2 macs */
23 #define MTK_MAX_DEVS 2
24
25 -/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
26 - * characteristics
27 +/* struct mtk_pcs - This structure holds each sgmii regmap and associated
28 + * data
29 * @regmap: The register map pointing at the range used to setup
30 * SGMII modes
31 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
32 */
33 +struct mtk_pcs {
34 + struct regmap *regmap;
35 + u32 ana_rgc3;
36 +};
37
38 +/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
39 + * characteristics
40 + * @pcs Array of individual PCS structures
41 + */
42 struct mtk_sgmii {
43 - struct regmap *regmap[MTK_MAX_DEVS];
44 - u32 ana_rgc3;
45 + struct mtk_pcs pcs[MTK_MAX_DEVS];
46 };
47
48 /* struct mtk_eth - This is the main datasructure for holding the state
49 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
50 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
51 @@ -9,90 +9,71 @@
52
53 #include <linux/mfd/syscon.h>
54 #include <linux/of.h>
55 +#include <linux/phylink.h>
56 #include <linux/regmap.h>
57
58 #include "mtk_eth_soc.h"
59
60 -int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
61 -{
62 - struct device_node *np;
63 - int i;
64 -
65 - ss->ana_rgc3 = ana_rgc3;
66 -
67 - for (i = 0; i < MTK_MAX_DEVS; i++) {
68 - np = of_parse_phandle(r, "mediatek,sgmiisys", i);
69 - if (!np)
70 - break;
71 -
72 - ss->regmap[i] = syscon_node_to_regmap(np);
73 - of_node_put(np);
74 - if (IS_ERR(ss->regmap[i]))
75 - return PTR_ERR(ss->regmap[i]);
76 - }
77 -
78 - return 0;
79 -}
80 -
81 /* For SGMII interface mode */
82 -static int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
83 +static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
84 {
85 unsigned int val;
86
87 - if (!ss->regmap[id])
88 + if (!mpcs->regmap)
89 return -EINVAL;
90
91 /* Setup the link timer and QPHY power up inside SGMIISYS */
92 - regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
93 + regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
94 SGMII_LINK_TIMER_DEFAULT);
95
96 - regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
97 + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
98 val |= SGMII_REMOTE_FAULT_DIS;
99 - regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
100 + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
101
102 - regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
103 + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
104 val |= SGMII_AN_RESTART;
105 - regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
106 + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
107
108 - regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
109 + regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
110 val &= ~SGMII_PHYA_PWD;
111 - regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
112 + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
113
114 return 0;
115 +
116 }
117
118 /* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
119 * fixed speed.
120 */
121 -static int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
122 - phy_interface_t interface)
123 +static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
124 + phy_interface_t interface)
125 {
126 unsigned int val;
127
128 - if (!ss->regmap[id])
129 + if (!mpcs->regmap)
130 return -EINVAL;
131
132 - regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
133 + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
134 val &= ~RG_PHY_SPEED_MASK;
135 if (interface == PHY_INTERFACE_MODE_2500BASEX)
136 val |= RG_PHY_SPEED_3_125G;
137 - regmap_write(ss->regmap[id], ss->ana_rgc3, val);
138 + regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
139
140 /* Disable SGMII AN */
141 - regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
142 + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
143 val &= ~SGMII_AN_ENABLE;
144 - regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
145 + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
146
147 /* Set the speed etc but leave the duplex unchanged */
148 - regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
149 + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
150 val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
151 val |= SGMII_SPEED_1000;
152 - regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
153 + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
154
155 /* Release PHYA power down state */
156 - regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
157 + regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
158 val &= ~SGMII_PHYA_PWD;
159 - regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
160 + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
161
162 return 0;
163 }
164 @@ -100,44 +81,76 @@ static int mtk_sgmii_setup_mode_force(st
165 int mtk_sgmii_config(struct mtk_sgmii *ss, int id, unsigned int mode,
166 phy_interface_t interface)
167 {
168 + struct mtk_pcs *mpcs = &ss->pcs[id];
169 int err = 0;
170
171 /* Setup SGMIISYS with the determined property */
172 if (interface != PHY_INTERFACE_MODE_SGMII)
173 - err = mtk_sgmii_setup_mode_force(ss, id, interface);
174 + err = mtk_pcs_setup_mode_force(mpcs, interface);
175 else if (phylink_autoneg_inband(mode))
176 - err = mtk_sgmii_setup_mode_an(ss, id);
177 + err = mtk_pcs_setup_mode_an(mpcs);
178
179 return err;
180 }
181
182 -/* For 1000BASE-X and 2500BASE-X interface modes */
183 -void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
184 +static void mtk_pcs_restart_an(struct mtk_pcs *mpcs)
185 +{
186 + unsigned int val;
187 +
188 + if (!mpcs->regmap)
189 + return;
190 +
191 + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
192 + val |= SGMII_AN_RESTART;
193 + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
194 +}
195 +
196 +static void mtk_pcs_link_up(struct mtk_pcs *mpcs, int speed, int duplex)
197 {
198 unsigned int val;
199
200 /* SGMII force duplex setting */
201 - regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
202 + regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
203 val &= ~SGMII_DUPLEX_FULL;
204 if (duplex == DUPLEX_FULL)
205 val |= SGMII_DUPLEX_FULL;
206
207 - regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
208 + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
209 +}
210 +
211 +/* For 1000BASE-X and 2500BASE-X interface modes */
212 +void mtk_sgmii_link_up(struct mtk_sgmii *ss, int id, int speed, int duplex)
213 +{
214 + mtk_pcs_link_up(&ss->pcs[id], speed, duplex);
215 +}
216 +
217 +int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
218 +{
219 + struct device_node *np;
220 + int i;
221 +
222 + for (i = 0; i < MTK_MAX_DEVS; i++) {
223 + np = of_parse_phandle(r, "mediatek,sgmiisys", i);
224 + if (!np)
225 + break;
226 +
227 + ss->pcs[i].ana_rgc3 = ana_rgc3;
228 + ss->pcs[i].regmap = syscon_node_to_regmap(np);
229 + of_node_put(np);
230 + if (IS_ERR(ss->pcs[i].regmap))
231 + return PTR_ERR(ss->pcs[i].regmap);
232 + }
233 +
234 + return 0;
235 }
236
237 void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id)
238 {
239 - struct mtk_sgmii *ss = eth->sgmii;
240 - unsigned int val, sid;
241 + unsigned int sid;
242
243 /* Decide how GMAC and SGMIISYS be mapped */
244 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
245 0 : mac_id;
246
247 - if (!ss->regmap[sid])
248 - return;
249 -
250 - regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
251 - val |= SGMII_AN_RESTART;
252 - regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);
253 + mtk_pcs_restart_an(&eth->sgmii->pcs[sid]);
254 }
Staging tree of Jonas Gorski