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1 From 485d11cfa7df2d2deb39c9b3455cebcb1a85cea2 Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Thu, 25 Jul 2024 14:36:32 +0100
4 Subject: [PATCH 1199/1215] drm/vc4: Disable the 2pixel/clock odd timings
5 workaround for interlaced
6
7 Whilst BCM2712 does fix using odd horizontal timings, it doesn't
8 work with interlaced modes.
9
10 Drop the workaround for interlaced modes and revert to the same
11 behaviour as BCM2711.
12
13 https://github.com/raspberrypi/linux/issues/6281
14
15 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
16 ---
17 drivers/gpu/drm/vc4/vc4_crtc.c | 20 +++++++++++++++++---
18 drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
19 drivers/gpu/drm/vc4/vc4_hdmi.c | 8 +++++++-
20 drivers/gpu/drm/vc4/vc4_hdmi.h | 4 ++++
21 4 files changed, 30 insertions(+), 4 deletions(-)
22
23 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
24 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
25 @@ -378,7 +378,9 @@ static void vc4_crtc_config_pv(struct dr
26 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
27 bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
28 u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
29 - u8 ppc = pv_data->pixels_per_clock;
30 + u8 ppc = (mode->flags & DRM_MODE_FLAG_INTERLACE) ?
31 + pv_data->pixels_per_clock_int :
32 + pv_data->pixels_per_clock;
33
34 u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
35 u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
36 @@ -443,7 +445,8 @@ static void vc4_crtc_config_pv(struct dr
37 */
38 CRTC_WRITE(PV_V_CONTROL,
39 PV_VCONTROL_CONTINUOUS |
40 - (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
41 + (vc4->gen >= VC4_GEN_6 && ppc == 1 ?
42 + PV_VCONTROL_ODD_TIMING : 0) |
43 (is_dsi ? PV_VCONTROL_DSI : 0) |
44 PV_VCONTROL_INTERLACE |
45 (odd_field_first
46 @@ -455,7 +458,8 @@ static void vc4_crtc_config_pv(struct dr
47 } else {
48 CRTC_WRITE(PV_V_CONTROL,
49 PV_VCONTROL_CONTINUOUS |
50 - (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
51 + (vc4->gen >= VC4_GEN_6 && ppc == 1 ?
52 + PV_VCONTROL_ODD_TIMING : 0) |
53 (is_dsi ? PV_VCONTROL_DSI : 0));
54 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
55 }
56 @@ -1223,6 +1227,7 @@ const struct vc4_pv_data bcm2835_pv0_dat
57 },
58 .fifo_depth = 64,
59 .pixels_per_clock = 1,
60 + .pixels_per_clock_int = 1,
61 .encoder_types = {
62 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
63 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
64 @@ -1238,6 +1243,7 @@ const struct vc4_pv_data bcm2835_pv1_dat
65 },
66 .fifo_depth = 64,
67 .pixels_per_clock = 1,
68 + .pixels_per_clock_int = 1,
69 .encoder_types = {
70 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
71 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
72 @@ -1253,6 +1259,7 @@ const struct vc4_pv_data bcm2835_pv2_dat
73 },
74 .fifo_depth = 64,
75 .pixels_per_clock = 1,
76 + .pixels_per_clock_int = 1,
77 .encoder_types = {
78 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
79 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
80 @@ -1268,6 +1275,7 @@ const struct vc4_pv_data bcm2711_pv0_dat
81 },
82 .fifo_depth = 64,
83 .pixels_per_clock = 1,
84 + .pixels_per_clock_int = 1,
85 .encoder_types = {
86 [0] = VC4_ENCODER_TYPE_DSI0,
87 [1] = VC4_ENCODER_TYPE_DPI,
88 @@ -1283,6 +1291,7 @@ const struct vc4_pv_data bcm2711_pv1_dat
89 },
90 .fifo_depth = 64,
91 .pixels_per_clock = 1,
92 + .pixels_per_clock_int = 1,
93 .encoder_types = {
94 [0] = VC4_ENCODER_TYPE_DSI1,
95 [1] = VC4_ENCODER_TYPE_SMI,
96 @@ -1298,6 +1307,7 @@ const struct vc4_pv_data bcm2711_pv2_dat
97 },
98 .fifo_depth = 256,
99 .pixels_per_clock = 2,
100 + .pixels_per_clock_int = 2,
101 .encoder_types = {
102 [0] = VC4_ENCODER_TYPE_HDMI0,
103 },
104 @@ -1312,6 +1322,7 @@ const struct vc4_pv_data bcm2711_pv3_dat
105 },
106 .fifo_depth = 64,
107 .pixels_per_clock = 1,
108 + .pixels_per_clock_int = 1,
109 .encoder_types = {
110 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
111 },
112 @@ -1326,6 +1337,7 @@ const struct vc4_pv_data bcm2711_pv4_dat
113 },
114 .fifo_depth = 64,
115 .pixels_per_clock = 2,
116 + .pixels_per_clock_int = 2,
117 .encoder_types = {
118 [0] = VC4_ENCODER_TYPE_HDMI1,
119 },
120 @@ -1339,6 +1351,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
121 },
122 .fifo_depth = 64,
123 .pixels_per_clock = 1,
124 + .pixels_per_clock_int = 2,
125 .encoder_types = {
126 [0] = VC4_ENCODER_TYPE_HDMI0,
127 },
128 @@ -1352,6 +1365,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
129 },
130 .fifo_depth = 64,
131 .pixels_per_clock = 1,
132 + .pixels_per_clock_int = 2,
133 .encoder_types = {
134 [0] = VC4_ENCODER_TYPE_HDMI1,
135 },
136 --- a/drivers/gpu/drm/vc4/vc4_drv.h
137 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
138 @@ -569,6 +569,8 @@ struct vc4_pv_data {
139
140 /* Number of pixels output per clock period */
141 u8 pixels_per_clock;
142 + /* Number of pixels output per clock period when in an interlaced mode */
143 + u8 pixels_per_clock_int;
144
145 enum vc4_encoder_type encoder_types[4];
146 };
147 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
148 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
149 @@ -2263,7 +2263,9 @@ static int vc4_hdmi_encoder_atomic_check
150 unsigned long long tmds_bit_rate;
151 int ret;
152
153 - if (vc4_hdmi->variant->unsupported_odd_h_timings) {
154 + if (vc4_hdmi->variant->unsupported_odd_h_timings ||
155 + (vc4_hdmi->variant->unsupported_int_odd_h_timings &&
156 + (mode->flags & DRM_MODE_FLAG_INTERLACE))) {
157 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
158 /* Only try to fixup DBLCLK modes to get 480i and 576i
159 * working.
160 @@ -3974,6 +3976,7 @@ static const struct vc4_hdmi_variant bcm
161 PHY_LANE_CK,
162 },
163 .unsupported_odd_h_timings = true,
164 + .unsupported_int_odd_h_timings = true,
165 .external_irq_controller = true,
166
167 .init_resources = vc5_hdmi_init_resources,
168 @@ -4003,6 +4006,7 @@ static const struct vc4_hdmi_variant bcm
169 PHY_LANE_2,
170 },
171 .unsupported_odd_h_timings = true,
172 + .unsupported_int_odd_h_timings = true,
173 .external_irq_controller = true,
174
175 .init_resources = vc5_hdmi_init_resources,
176 @@ -4032,6 +4036,7 @@ static const struct vc4_hdmi_variant bcm
177 PHY_LANE_CK,
178 },
179 .unsupported_odd_h_timings = false,
180 + .unsupported_int_odd_h_timings = true,
181 .external_irq_controller = true,
182
183 .init_resources = vc5_hdmi_init_resources,
184 @@ -4059,6 +4064,7 @@ static const struct vc4_hdmi_variant bcm
185 PHY_LANE_CK,
186 },
187 .unsupported_odd_h_timings = false,
188 + .unsupported_int_odd_h_timings = true,
189 .external_irq_controller = true,
190
191 .init_resources = vc5_hdmi_init_resources,
192 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
193 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
194 @@ -49,6 +49,10 @@ struct vc4_hdmi_variant {
195
196 /* The BCM2711 cannot deal with odd horizontal pixel timings */
197 bool unsupported_odd_h_timings;
198 + /* The BCM2712 can handle odd horizontal pixel timings, but not in
199 + * interlaced modes
200 + */
201 + bool unsupported_int_odd_h_timings;
202
203 /*
204 * The BCM2711 CEC/hotplug IRQ controller is shared between the
Staging tree of Christian Marangi