git.openwrt.org Git - openwrt/staging/lynxis.git/blob

   1 From fb5e436843614f93b30aec0a2a00e5e59a133aab Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
   3 Date: Sat, 15 May 2021 17:44:24 +0200
   4 Subject: [PATCH] wtmi: uart: fix UART baudrate divisor calculation
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The UART code uses the xtal clock as parent for UART baudrate
  10 generation, but it assumes that xtal runs at 25 MHz, which isn't
  11 necessarily the case for all A3720 boards.
  12
  13 Use get_ref_clk() to determine xtal clock rate.
  14
  15 Use rounding division to compute the divisor value.
  16
  17 Signed-off-by: Marek Behún <marek.behun@nic.cz>
  18 Suggested-by: Pali Rohár <pali@kernel.org>
  19 ---
  20  wtmi/types.h | 5 +++++
  21  wtmi/uart.c  | 7 ++++---
  22  2 files changed, 9 insertions(+), 3 deletions(-)
  23
  24 diff --git a/wtmi/types.h b/wtmi/types.h
  25 index 7a6c6c6..ea873fc 100644
  26 --- a/wtmi/types.h
  27 +++ b/wtmi/types.h
  28 @@ -47,4 +47,9 @@ typedef u32                   size_t;
  29
  30  #define maybe_unused __attribute__((unused))
  31
  32 +static inline u32 div_round_closest_u32(u32 x, u32 d)
  33 +{
  34 +       return (x + d / 2) / d;
  35 +}
  36 +
  37  #endif /* __TYPES_H */
  38 diff --git a/wtmi/uart.c b/wtmi/uart.c
  39 index d40633d..75864b5 100644
  40 --- a/wtmi/uart.c
  41 +++ b/wtmi/uart.c
  42 @@ -40,8 +40,6 @@
  43  #include "stdio.h"
  44  #include "debug.h"
  45
  46 -#define UART_CLOCK_FREQ                25804800
  47 -
  48  const struct uart_info uart1_info = {
  49         .rx     = 0xc0012000,
  50         .tx     = 0xc0012004,
  51 @@ -76,8 +74,11 @@ void uart_set_stdio(const struct uart_info *info)
  52
  53  void uart_reset(const struct uart_info *info, unsigned int baudrate)
  54  {
  55 +       u32 parent_rate = get_ref_clk() * 1000000;
  56 +
  57         /* set baudrate */
  58 -       writel((UART_CLOCK_FREQ / baudrate / 16), info->baud);
  59 +       writel(div_round_closest_u32(parent_rate, baudrate * 16), info->baud);
  60 +
  61         /* set Programmable Oversampling Stack to 0, UART defaults to 16X scheme */
  62         writel(0, info->possr);
  63
  64 --
  65 2.30.2
  66