4b20932f53872b520bb4a102d5a643f4e2e501fe
[openwrt/staging/aparcar.git] /
1 Instead of defining an enumeration with the FW specific values for the
2 different clock rates, use the actual frequency instead. Also add a
3 boolean to specify whether the clock is XTAL or not.
4
5 Change all board files to reflect this.
6
7 Additionally, this reverts commit 26f45c (ARM: OMAP2+: Legacy support
8 for wl12xx when booted with devicetree), since this is not be needed
9 anymore, now that DT support for WiLink is implemented.
10
11 Cc: Tony Lindgren <tony@atomide.com>
12 Cc: Sekhar Nori <nsekhar@ti.com>
13 Signed-off-by: Luciano Coelho <coelho@ti.com>
14 Reviewed-by: Felipe Balbi <balbi@ti.com>
15
16 --- a/drivers/net/wireless/ti/wl12xx/main.c
17 +++ b/drivers/net/wireless/ti/wl12xx/main.c
18 @@ -1711,6 +1711,43 @@ static struct ieee80211_sta_ht_cap wl12x
19 },
20 };
21
22 +static const struct wl12xx_clock wl12xx_refclock_table[] = {
23 + { 19200000, false, WL12XX_REFCLOCK_19 },
24 + { 26000000, false, WL12XX_REFCLOCK_26 },
25 + { 26000000, true, WL12XX_REFCLOCK_26_XTAL },
26 + { 38400000, false, WL12XX_REFCLOCK_38 },
27 + { 38400000, true, WL12XX_REFCLOCK_38_XTAL },
28 + { 52000000, false, WL12XX_REFCLOCK_52 },
29 + { 0, false, 0 }
30 +};
31 +
32 +static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
33 + { 16368000, true, WL12XX_TCXOCLOCK_16_368 },
34 + { 16800000, true, WL12XX_TCXOCLOCK_16_8 },
35 + { 19200000, true, WL12XX_TCXOCLOCK_19_2 },
36 + { 26000000, true, WL12XX_TCXOCLOCK_26 },
37 + { 32736000, true, WL12XX_TCXOCLOCK_32_736 },
38 + { 33600000, true, WL12XX_TCXOCLOCK_33_6 },
39 + { 38400000, true, WL12XX_TCXOCLOCK_38_4 },
40 + { 52000000, true, WL12XX_TCXOCLOCK_52 },
41 + { 0, false, 0 }
42 +};
43 +
44 +static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
45 + u32 freq, bool xtal)
46 +{
47 + int i = 0;
48 +
49 + while(table[i].freq != 0) {
50 + if ((table[i].freq == freq) &&
51 + (table[i].xtal == xtal))
52 + return table[i].hw_idx;
53 + i++;
54 + };
55 +
56 + return -EINVAL;
57 +}
58 +
59 static int wl12xx_setup(struct wl1271 *wl)
60 {
61 struct wl12xx_priv *priv = wl->priv;
62 @@ -1732,7 +1769,16 @@ static int wl12xx_setup(struct wl1271 *w
63 wl12xx_conf_init(wl);
64
65 if (!fref_param) {
66 - priv->ref_clock = pdata->board_ref_clock;
67 + priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
68 + pdata->ref_clock_freq,
69 + pdata->ref_clock_xtal);
70 + if (priv->ref_clock < 0) {
71 + wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
72 + pdata->ref_clock_freq,
73 + pdata->ref_clock_xtal ? "XTAL" : "not XTAL");
74 +
75 + return priv->ref_clock;
76 + }
77 } else {
78 if (!strcmp(fref_param, "19.2"))
79 priv->ref_clock = WL12XX_REFCLOCK_19;
80 @@ -1751,7 +1797,15 @@ static int wl12xx_setup(struct wl1271 *w
81 }
82
83 if (!tcxo_param) {
84 - priv->tcxo_clock = pdata->board_tcxo_clock;
85 + priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
86 + pdata->tcxo_clock_freq,
87 + true);
88 + if (priv->tcxo_clock < 0) {
89 + wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
90 + pdata->tcxo_clock_freq);
91 +
92 + return priv->tcxo_clock;
93 + }
94 } else {
95 if (!strcmp(tcxo_param, "19.2"))
96 priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
97 --- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
98 +++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
99 @@ -79,4 +79,32 @@ struct wl12xx_priv {
100 struct wl127x_rx_mem_pool_addr *rx_mem_addr;
101 };
102
103 +/* Reference clock values */
104 +enum {
105 + WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
106 + WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
107 + WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
108 + WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
109 + WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
110 + WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
111 +};
112 +
113 +/* TCXO clock values */
114 +enum {
115 + WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
116 + WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
117 + WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
118 + WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
119 + WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
120 + WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
121 + WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */
122 + WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */
123 +};
124 +
125 +struct wl12xx_clock {
126 + u32 freq;
127 + bool xtal;
128 + u8 hw_idx;
129 +};
130 +
131 #endif /* __WL12XX_PRIV_H__ */