git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 5f15d392dcb4aa250a63d6f2c5adfc26c0aedc78 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Tue, 2 Nov 2021 19:30:41 +0100
   4 Subject: net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled
   5
   6 Some device set MAC06 exchange in the bootloader. This cause some
   7 problem as we don't support this strange mode and we just set the port6
   8 as the primary CPU port. With MAC06 exchange, PAD0 reg configure port6
   9 instead of port0. Add an extra check and explicitly disable MAC06 exchange
  10 to correctly configure the port PAD config.
  11
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Fixes: 3fcf734aa482 ("net: dsa: qca8k: add support for cpu port 6")
  14 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17  drivers/net/dsa/qca8k.c | 8 ++++++++
  18  drivers/net/dsa/qca8k.h | 1 +
  19  2 files changed, 9 insertions(+)
  20
  21 --- a/drivers/net/dsa/qca8k.c
  22 +++ b/drivers/net/dsa/qca8k.c
  23 @@ -1109,6 +1109,14 @@ qca8k_setup(struct dsa_switch *ds)
  24         if (ret)
  25                 return ret;
  26
  27 +       /* Make sure MAC06 is disabled */
  28 +       ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,
  29 +                             QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
  30 +       if (ret) {
  31 +               dev_err(priv->dev, "failed disabling MAC06 exchange");
  32 +               return ret;
  33 +       }
  34 +
  35         /* Enable CPU Port */
  36         ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
  37                             QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
  38 --- a/drivers/net/dsa/qca8k.h
  39 +++ b/drivers/net/dsa/qca8k.h
  40 @@ -34,6 +34,7 @@
  41  #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK               GENMASK(15, 8)
  42  #define   QCA8K_MASK_CTRL_DEVICE_ID(x)                 ((x) >> 8)
  43  #define QCA8K_REG_PORT0_PAD_CTRL                       0x004
  44 +#define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN            BIT(31)
  45  #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE     BIT(19)
  46  #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE     BIT(18)
  47  #define QCA8K_REG_PORT5_PAD_CTRL                       0x008