git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 19 Mar 2023 12:56:52 +0000
   4 Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
   5  schema
   6
   7 Convert mediatek,sgmiiisys bindings to DT schema format.
   8 Add maintainer Matthias Brugger, no maintainers were listed in the
   9 original documentation.
  10 As this node is also referenced by the Ethernet controller and used
  11 as SGMII PCS add this fact to the description.
  12 Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
  13 more appropriate given that the great majority of registers are related
  14 to SGMII PCS functionality and only one register represents clock bits.
  15
  16 Reviewed-by: Rob Herring <robh@kernel.org>
  17 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  18 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  19 ---
  20  .../arm/mediatek/mediatek,sgmiisys.txt        | 27 ----------
  21  .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 49 +++++++++++++++++++
  22  2 files changed, 49 insertions(+), 27 deletions(-)
  23  delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
  24  create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
  25
  26 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
  27 +++ /dev/null
  28 @@ -1,27 +0,0 @@
  29 -MediaTek SGMIISYS controller
  30 -============================
  31 -
  32 -The MediaTek SGMIISYS controller provides various clocks to the system.
  33 -
  34 -Required Properties:
  35 -
  36 -- compatible: Should be:
  37 -       - "mediatek,mt7622-sgmiisys", "syscon"
  38 -       - "mediatek,mt7629-sgmiisys", "syscon"
  39 -       - "mediatek,mt7981-sgmiisys_0", "syscon"
  40 -       - "mediatek,mt7981-sgmiisys_1", "syscon"
  41 -       - "mediatek,mt7986-sgmiisys_0", "syscon"
  42 -       - "mediatek,mt7986-sgmiisys_1", "syscon"
  43 -- #clock-cells: Must be 1
  44 -
  45 -The SGMIISYS controller uses the common clk binding from
  46 -Documentation/devicetree/bindings/clock/clock-bindings.txt
  47 -The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  48 -
  49 -Example:
  50 -
  51 -sgmiisys: sgmiisys@1b128000 {
  52 -       compatible = "mediatek,mt7622-sgmiisys", "syscon";
  53 -       reg = <0 0x1b128000 0 0x1000>;
  54 -       #clock-cells = <1>;
  55 -};
  56 --- /dev/null
  57 +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
  58 @@ -0,0 +1,49 @@
  59 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  60 +%YAML 1.2
  61 +---
  62 +$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
  63 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  64 +
  65 +title: MediaTek SGMIISYS Controller
  66 +
  67 +maintainers:
  68 +  - Matthias Brugger <matthias.bgg@gmail.com>
  69 +
  70 +description:
  71 +  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
  72 +  to the ethernet subsystem to which it is attached.
  73 +
  74 +properties:
  75 +  compatible:
  76 +    items:
  77 +      - enum:
  78 +          - mediatek,mt7622-sgmiisys
  79 +          - mediatek,mt7629-sgmiisys
  80 +          - mediatek,mt7986-sgmiisys_0
  81 +          - mediatek,mt7986-sgmiisys_1
  82 +      - const: syscon
  83 +
  84 +  reg:
  85 +    maxItems: 1
  86 +
  87 +  '#clock-cells':
  88 +    const: 1
  89 +
  90 +required:
  91 +  - compatible
  92 +  - reg
  93 +  - '#clock-cells'
  94 +
  95 +additionalProperties: false
  96 +
  97 +examples:
  98 +  - |
  99 +    soc {
 100 +      #address-cells = <2>;
 101 +      #size-cells = <2>;
 102 +      sgmiisys: syscon@1b128000 {
 103 +        compatible = "mediatek,mt7622-sgmiisys", "syscon";
 104 +        reg = <0 0x1b128000 0 0x1000>;
 105 +        #clock-cells = <1>;
 106 +      };
 107 +    };