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1 From c9ad8286ca39c2545f6a6851a8ede8488a9263f3 Mon Sep 17 00:00:00 2001
2 From: Pavithra R <quic_pavir@quicinc.com>
3 Date: Tue, 11 Jun 2024 00:00:46 +0530
4 Subject: [PATCH 44/50] net: ethernet: qualcomm: Add module parameters for
5 driver tunings
6
7 Add module params and corresponding functionality for Tx/Rx
8 mitigation timer/packet count, napi budget and tx requeue stop.
9
10 Change-Id: I1717559c931bba4f355ee06ab89f289818400ca2
11 Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
12 ---
13 drivers/net/ethernet/qualcomm/ppe/edma.c | 35 +++++++++++++++++++
14 .../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 29 +++++++++++++--
15 .../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 21 +++++++++++
16 .../net/ethernet/qualcomm/ppe/edma_cfg_tx.c | 29 +++++++++++++--
17 .../net/ethernet/qualcomm/ppe/edma_cfg_tx.h | 16 +++++++++
18 drivers/net/ethernet/qualcomm/ppe/edma_rx.h | 4 +++
19 drivers/net/ethernet/qualcomm/ppe/edma_tx.h | 4 +++
20 7 files changed, 134 insertions(+), 4 deletions(-)
21
22 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma.c b/drivers/net/ethernet/qualcomm/ppe/edma.c
23 index 0e16f8ab545f..ae9ca528fd55 100644
24 --- a/drivers/net/ethernet/qualcomm/ppe/edma.c
25 +++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
26 @@ -38,6 +38,38 @@ static int rx_buff_size;
27 module_param(rx_buff_size, int, 0640);
28 MODULE_PARM_DESC(rx_buff_size, "Rx Buffer size for Jumbo MRU value (default:0)");
29
30 +int edma_rx_napi_budget = EDMA_RX_NAPI_WORK_DEF;
31 +module_param(edma_rx_napi_budget, int, 0444);
32 +MODULE_PARM_DESC(edma_rx_napi_budget, "Rx NAPI budget (default:128, min:16, max:512)");
33 +
34 +int edma_tx_napi_budget = EDMA_TX_NAPI_WORK_DEF;
35 +module_param(edma_tx_napi_budget, int, 0444);
36 +MODULE_PARM_DESC(edma_tx_napi_budget, "Tx NAPI budget (default:512 for ipq95xx, min:16, max:512)");
37 +
38 +int edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF;
39 +module_param(edma_rx_mitigation_pkt_cnt, int, 0444);
40 +MODULE_PARM_DESC(edma_rx_mitigation_pkt_cnt,
41 + "Rx mitigation packet count value (default:16, min:0, max: 256)");
42 +
43 +s32 edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF;
44 +module_param(edma_rx_mitigation_timer, int, 0444);
45 +MODULE_PARM_DESC(edma_dp_rx_mitigation_timer,
46 + "Rx mitigation timer value in microseconds (default:25, min:0, max: 1000)");
47 +
48 +int edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF;
49 +module_param(edma_tx_mitigation_timer, int, 0444);
50 +MODULE_PARM_DESC(edma_tx_mitigation_timer,
51 + "Tx mitigation timer value in microseconds (default:250, min:0, max: 1000)");
52 +
53 +int edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF;
54 +module_param(edma_tx_mitigation_pkt_cnt, int, 0444);
55 +MODULE_PARM_DESC(edma_tx_mitigation_pkt_cnt,
56 + "Tx mitigation packet count value (default:16, min:0, max: 256)");
57 +
58 +static int tx_requeue_stop;
59 +module_param(tx_requeue_stop, int, 0640);
60 +MODULE_PARM_DESC(tx_requeue_stop, "Disable Tx requeue function (default:0)");
61 +
62 /* Priority to multi-queue mapping. */
63 static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = {
64 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7};
65 @@ -828,7 +860,10 @@ int edma_setup(struct ppe_device *ppe_dev)
66 edma_ctx->hw_info = &ipq9574_hw_info;
67 edma_ctx->ppe_dev = ppe_dev;
68 edma_ctx->rx_buf_size = rx_buff_size;
69 +
70 edma_ctx->tx_requeue_stop = false;
71 + if (tx_requeue_stop != 0)
72 + edma_ctx->tx_requeue_stop = true;
73
74 /* Configure the EDMA common clocks. */
75 ret = edma_clock_init();
76 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
77 index 18e4ada6a076..bf8854976328 100644
78 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
79 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
80 @@ -166,6 +166,24 @@ static void edma_cfg_rx_desc_ring_configure(struct edma_rxdesc_ring *rxdesc_ring
81 reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->ring_id);
82 regmap_write(regmap, reg, data);
83
84 + /* Validate mitigation timer value */
85 + if (edma_rx_mitigation_timer < EDMA_RX_MITIGATION_TIMER_MIN ||
86 + edma_rx_mitigation_timer > EDMA_RX_MITIGATION_TIMER_MAX) {
87 + pr_err("Invalid Rx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n",
88 + edma_rx_mitigation_timer, rxdesc_ring->ring_id,
89 + EDMA_RX_MITIGATION_TIMER_DEF);
90 + edma_rx_mitigation_timer = EDMA_RX_MITIGATION_TIMER_DEF;
91 + }
92 +
93 + /* Validate mitigation packet count value */
94 + if (edma_rx_mitigation_pkt_cnt < EDMA_RX_MITIGATION_PKT_CNT_MIN ||
95 + edma_rx_mitigation_pkt_cnt > EDMA_RX_MITIGATION_PKT_CNT_MAX) {
96 + pr_err("Invalid Rx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n",
97 + edma_rx_mitigation_timer, rxdesc_ring->ring_id,
98 + EDMA_RX_MITIGATION_PKT_CNT_DEF);
99 + edma_rx_mitigation_pkt_cnt = EDMA_RX_MITIGATION_PKT_CNT_DEF;
100 + }
101 +
102 /* Configure the Mitigation timer */
103 data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_RX_MITIGATION_TIMER_DEF,
104 ppe_dev->clk_rate / MHZ);
105 @@ -176,7 +194,7 @@ static void edma_cfg_rx_desc_ring_configure(struct edma_rxdesc_ring *rxdesc_ring
106 regmap_write(regmap, reg, data);
107
108 /* Configure the Mitigation packet count */
109 - data = (EDMA_RX_MITIGATION_PKT_CNT_DEF & EDMA_RXDESC_LOW_THRE_MASK)
110 + data = (edma_rx_mitigation_pkt_cnt & EDMA_RXDESC_LOW_THRE_MASK)
111 << EDMA_RXDESC_LOW_THRE_SHIFT;
112 pr_debug("EDMA Rx mitigation packet count value: %d\n", data);
113 reg = EDMA_BASE_OFFSET + EDMA_REG_RXDESC_UGT_THRE(rxdesc_ring->ring_id);
114 @@ -915,6 +933,13 @@ void edma_cfg_rx_napi_add(void)
115 struct edma_ring_info *rx = hw_info->rx;
116 u32 i;
117
118 + if (edma_rx_napi_budget < EDMA_RX_NAPI_WORK_MIN ||
119 + edma_rx_napi_budget > EDMA_RX_NAPI_WORK_MAX) {
120 + pr_err("Incorrect Rx NAPI budget: %d, setting to default: %d",
121 + edma_rx_napi_budget, hw_info->napi_budget_rx);
122 + edma_rx_napi_budget = hw_info->napi_budget_rx;
123 + }
124 +
125 for (i = 0; i < rx->num_rings; i++) {
126 struct edma_rxdesc_ring *rxdesc_ring = &edma_ctx->rx_rings[i];
127
128 @@ -923,7 +948,7 @@ void edma_cfg_rx_napi_add(void)
129 rxdesc_ring->napi_added = true;
130 }
131
132 - netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", hw_info->napi_budget_rx);
133 + netdev_dbg(edma_ctx->dummy_dev, "Rx NAPI budget: %d\n", edma_rx_napi_budget);
134 }
135
136 /**
137 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
138 index 3c84ef4ea85c..bd897dba286a 100644
139 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
140 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
141 @@ -5,6 +5,15 @@
142 #ifndef __EDMA_CFG_RX__
143 #define __EDMA_CFG_RX__
144
145 +/* Rx default NAPI budget */
146 +#define EDMA_RX_NAPI_WORK_DEF 128
147 +
148 +/* RX minimum NAPI budget */
149 +#define EDMA_RX_NAPI_WORK_MIN 16
150 +
151 +/* Rx maximum NAPI budget */
152 +#define EDMA_RX_NAPI_WORK_MAX 512
153 +
154 /* SKB payload size used in page mode */
155 #define EDMA_RX_PAGE_MODE_SKB_SIZE 256
156
157 @@ -22,9 +31,21 @@
158 /* Rx mitigation timer's default value in microseconds */
159 #define EDMA_RX_MITIGATION_TIMER_DEF 25
160
161 +/* Rx mitigation timer's minimum value in microseconds */
162 +#define EDMA_RX_MITIGATION_TIMER_MIN 0
163 +
164 +/* Rx mitigation timer's maximum value in microseconds */
165 +#define EDMA_RX_MITIGATION_TIMER_MAX 1000
166 +
167 /* Rx mitigation packet count's default value */
168 #define EDMA_RX_MITIGATION_PKT_CNT_DEF 16
169
170 +/* Rx mitigation packet count's minimum value */
171 +#define EDMA_RX_MITIGATION_PKT_CNT_MIN 0
172 +
173 +/* Rx mitigation packet count's maximum value */
174 +#define EDMA_RX_MITIGATION_PKT_CNT_MAX 256
175 +
176 /* Default bitmap of cores for RPS to ARM cores */
177 #define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1)
178
179 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c
180 index f704c654b2cd..771acebdaf75 100644
181 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c
182 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.c
183 @@ -170,6 +170,24 @@ static void edma_cfg_txcmpl_ring_configure(struct edma_txcmpl_ring *txcmpl_ring)
184 reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id);
185 regmap_write(regmap, reg, EDMA_TXCMPL_RETMODE_OPAQUE);
186
187 + /* Validate mitigation timer value */
188 + if (edma_tx_mitigation_timer < EDMA_TX_MITIGATION_TIMER_MIN ||
189 + edma_tx_mitigation_timer > EDMA_TX_MITIGATION_TIMER_MAX) {
190 + pr_err("Invalid Tx mitigation timer configured:%d for ring:%d. Using the default timer value:%d\n",
191 + edma_tx_mitigation_timer, txcmpl_ring->id,
192 + EDMA_TX_MITIGATION_TIMER_DEF);
193 + edma_tx_mitigation_timer = EDMA_TX_MITIGATION_TIMER_DEF;
194 + }
195 +
196 + /* Validate mitigation packet count value */
197 + if (edma_tx_mitigation_pkt_cnt < EDMA_TX_MITIGATION_PKT_CNT_MIN ||
198 + edma_tx_mitigation_pkt_cnt > EDMA_TX_MITIGATION_PKT_CNT_MAX) {
199 + pr_err("Invalid Tx mitigation packet count configured:%d for ring:%d. Using the default packet counter value:%d\n",
200 + edma_tx_mitigation_timer, txcmpl_ring->id,
201 + EDMA_TX_MITIGATION_PKT_CNT_DEF);
202 + edma_tx_mitigation_pkt_cnt = EDMA_TX_MITIGATION_PKT_CNT_DEF;
203 + }
204 +
205 /* Configure the Mitigation timer. */
206 data = EDMA_MICROSEC_TO_TIMER_UNIT(EDMA_TX_MITIGATION_TIMER_DEF,
207 ppe_dev->clk_rate / MHZ);
208 @@ -180,7 +198,7 @@ static void edma_cfg_txcmpl_ring_configure(struct edma_txcmpl_ring *txcmpl_ring)
209 regmap_write(regmap, reg, data);
210
211 /* Configure the Mitigation packet count. */
212 - data = (EDMA_TX_MITIGATION_PKT_CNT_DEF & EDMA_TXCMPL_LOW_THRE_MASK)
213 + data = (edma_tx_mitigation_pkt_cnt & EDMA_TXCMPL_LOW_THRE_MASK)
214 << EDMA_TXCMPL_LOW_THRE_SHIFT;
215 pr_debug("EDMA Tx mitigation packet count value: %d\n", data);
216 reg = EDMA_BASE_OFFSET + EDMA_REG_TXCMPL_UGT_THRE(txcmpl_ring->id);
217 @@ -634,6 +652,13 @@ void edma_cfg_tx_napi_add(struct net_device *netdev, u32 port_id)
218 struct edma_txcmpl_ring *txcmpl_ring;
219 u32 i, ring_idx;
220
221 + if (edma_tx_napi_budget < EDMA_TX_NAPI_WORK_MIN ||
222 + edma_tx_napi_budget > EDMA_TX_NAPI_WORK_MAX) {
223 + pr_err("Incorrect Tx NAPI budget: %d, setting to default: %d",
224 + edma_tx_napi_budget, hw_info->napi_budget_tx);
225 + edma_tx_napi_budget = hw_info->napi_budget_tx;
226 + }
227 +
228 /* Adding tx napi for a interface with each queue. */
229 for_each_possible_cpu(i) {
230 ring_idx = ((port_id - 1) * num_possible_cpus()) + i;
231 @@ -644,5 +669,5 @@ void edma_cfg_tx_napi_add(struct net_device *netdev, u32 port_id)
232 netdev_dbg(netdev, "Napi added for txcmpl ring: %u\n", txcmpl_ring->id);
233 }
234
235 - netdev_dbg(netdev, "Tx NAPI budget: %d\n", hw_info->napi_budget_tx);
236 + netdev_dbg(netdev, "Tx NAPI budget: %d\n", edma_tx_napi_budget);
237 }
238 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h
239 index 4840c601fc86..608bbc5f93e8 100644
240 --- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h
241 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_tx.h
242 @@ -5,12 +5,28 @@
243 #ifndef __EDMA_CFG_TX__
244 #define __EDMA_CFG_TX__
245
246 +#define EDMA_TX_NAPI_WORK_DEF 512
247 +#define EDMA_TX_NAPI_WORK_MIN 16
248 +#define EDMA_TX_NAPI_WORK_MAX 512
249 +
250 /* Tx mitigation timer's default value. */
251 #define EDMA_TX_MITIGATION_TIMER_DEF 250
252
253 +/* Tx mitigation timer's minimum value in microseconds */
254 +#define EDMA_TX_MITIGATION_TIMER_MIN 0
255 +
256 +/* Tx mitigation timer's maximum value in microseconds */
257 +#define EDMA_TX_MITIGATION_TIMER_MAX 1000
258 +
259 /* Tx mitigation packet count default value. */
260 #define EDMA_TX_MITIGATION_PKT_CNT_DEF 16
261
262 +/* Tx mitigation packet count's minimum value */
263 +#define EDMA_TX_MITIGATION_PKT_CNT_MIN 0
264 +
265 +/* Tx mitigation packet count's maximum value */
266 +#define EDMA_TX_MITIGATION_PKT_CNT_MAX 256
267 +
268 void edma_cfg_tx_rings(void);
269 int edma_cfg_tx_rings_alloc(void);
270 void edma_cfg_tx_rings_cleanup(void);
271 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_rx.h b/drivers/net/ethernet/qualcomm/ppe/edma_rx.h
272 index 4a262a066808..0ef8138b4530 100644
273 --- a/drivers/net/ethernet/qualcomm/ppe/edma_rx.h
274 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_rx.h
275 @@ -281,6 +281,10 @@ struct edma_rxdesc_ring {
276 struct sk_buff *last;
277 };
278
279 +extern int edma_rx_napi_budget;
280 +extern int edma_rx_mitigation_timer;
281 +extern int edma_rx_mitigation_pkt_cnt;
282 +
283 irqreturn_t edma_rx_handle_irq(int irq, void *ctx);
284 int edma_rx_alloc_buffer(struct edma_rxfill_ring *rxfill_ring, int alloc_count);
285 int edma_rx_napi_poll(struct napi_struct *napi, int budget);
286 diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_tx.h b/drivers/net/ethernet/qualcomm/ppe/edma_tx.h
287 index c09a4e0f6a42..c4fa63321d1f 100644
288 --- a/drivers/net/ethernet/qualcomm/ppe/edma_tx.h
289 +++ b/drivers/net/ethernet/qualcomm/ppe/edma_tx.h
290 @@ -288,6 +288,10 @@ struct edma_txcmpl_ring {
291 bool napi_added;
292 };
293
294 +extern int edma_tx_napi_budget;
295 +extern int edma_tx_mitigation_timer;
296 +extern int edma_tx_mitigation_pkt_cnt;
297 +
298 enum edma_tx_status edma_tx_ring_xmit(struct net_device *netdev,
299 struct sk_buff *skb,
300 struct edma_txdesc_ring *txdesc_ring,
301 --
302 2.45.2
303
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