48854705849d8cb69f8d49d02bdfddb44ee495c6
[openwrt/staging/thess.git] /
1 From 79aaa6bcdc029ca754ee00c79865d2a92eba63ec Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.org>
3 Date: Wed, 31 Oct 2018 14:57:21 +0000
4 Subject: [PATCH 192/773] media: tc358743: Add support for 972Mbit/s link freq.
5
6 Adds register setups for running the CSI lanes at 972Mbit/s,
7 which allows 1080P50 UYVY down 2 lanes.
8
9 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
10 ---
11 drivers/media/i2c/tc358743.c | 47 +++++++++++++++++++++++++-----------
12 1 file changed, 33 insertions(+), 14 deletions(-)
13
14 --- a/drivers/media/i2c/tc358743.c
15 +++ b/drivers/media/i2c/tc358743.c
16 @@ -1967,6 +1967,7 @@ static int tc358743_probe_of(struct tc35
17 /*
18 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
19 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
20 + * 972 Mbps allows 1080P50 UYVY over 2-lane.
21 */
22 bps_pr_lane = 2 * endpoint->link_frequencies[0];
23 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
24 @@ -1979,23 +1980,41 @@ static int tc358743_probe_of(struct tc35
25 state->pdata.refclk_hz * state->pdata.pll_prd;
26
27 /*
28 - * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
29 - * link frequency). In principle it should be possible to calculate
30 + * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane
31 + * (297 MHz or 486 MHz link frequency).
32 + * In principle it should be possible to calculate
33 * them based on link frequency and resolution.
34 */
35 - if (bps_pr_lane != 594000000U)
36 + switch (bps_pr_lane) {
37 + default:
38 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
39 - state->pdata.lineinitcnt = 0xe80;
40 - state->pdata.lptxtimecnt = 0x003;
41 - /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
42 - state->pdata.tclk_headercnt = 0x1403;
43 - state->pdata.tclk_trailcnt = 0x00;
44 - /* ths-preparecnt: 3, ths-zerocnt: 1 */
45 - state->pdata.ths_headercnt = 0x0103;
46 - state->pdata.twakeup = 0x4882;
47 - state->pdata.tclk_postcnt = 0x008;
48 - state->pdata.ths_trailcnt = 0x2;
49 - state->pdata.hstxvregcnt = 0;
50 + case 594000000U:
51 + state->pdata.lineinitcnt = 0xe80;
52 + state->pdata.lptxtimecnt = 0x003;
53 + /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
54 + state->pdata.tclk_headercnt = 0x1403;
55 + state->pdata.tclk_trailcnt = 0x00;
56 + /* ths-preparecnt: 3, ths-zerocnt: 1 */
57 + state->pdata.ths_headercnt = 0x0103;
58 + state->pdata.twakeup = 0x4882;
59 + state->pdata.tclk_postcnt = 0x008;
60 + state->pdata.ths_trailcnt = 0x2;
61 + state->pdata.hstxvregcnt = 0;
62 + break;
63 + case 972000000U:
64 + state->pdata.lineinitcnt = 0x1b58;
65 + state->pdata.lptxtimecnt = 0x007;
66 + /* tclk-preparecnt: 6, tclk-zerocnt: 40 */
67 + state->pdata.tclk_headercnt = 0x2806;
68 + state->pdata.tclk_trailcnt = 0x00;
69 + /* ths-preparecnt: 6, ths-zerocnt: 8 */
70 + state->pdata.ths_headercnt = 0x0806;
71 + state->pdata.twakeup = 0x4268;
72 + state->pdata.tclk_postcnt = 0x008;
73 + state->pdata.ths_trailcnt = 0x5;
74 + state->pdata.hstxvregcnt = 0;
75 + break;
76 + }
77
78 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
79 GPIOD_OUT_LOW);