projects / openwrt / staging / ldir.git / blob
? search:


47ded1aeb5f25bb5a585ca7b26cad96082db4fad
[openwrt/staging/ldir.git] /
1 From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
2 From: Sam Shih <sam.shih@mediatek.com>
3 Date: Sun, 6 Nov 2022 09:01:13 +0100
4 Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
5 MT7986 SoC
6
7 Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
8 add SoC specify 'pull_type' attribute for bias configuration.
9
10 This patch add pull_type attribute to pinctrl-mt7986.c, and make
11 bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
12
13 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
14 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
15 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
16 Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
17 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
18 ---
19 drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
20 1 file changed, 56 insertions(+)
21
22 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
23 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
24 @@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
25 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
26 };
27
28 +static const unsigned int mt7986_pull_type[] = {
29 + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
30 + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
31 + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
32 + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
33 + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
34 + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
35 + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
36 + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
37 + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
38 + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
39 + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
40 + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
41 + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
42 + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
43 + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
44 + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
45 + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
46 + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
47 + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
48 + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
49 + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
50 + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
51 + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
52 + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
53 + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
54 + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
55 + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
56 + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
57 + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
58 + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
59 + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
60 + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
61 + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
62 + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
63 + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
64 + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
65 + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
66 + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
67 + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
68 + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
69 + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
70 + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
71 + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
72 + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
73 + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
74 + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
75 + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
76 + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
77 + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
78 + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
79 + MTK_PULL_PU_PD_TYPE,/*100*/
80 +};
81 +
82 static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
83 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
84 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
85 @@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
86 .ies_present = false,
87 .base_names = mt7986_pinctrl_register_base_names,
88 .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
89 + .pull_type = mt7986_pull_type,
90 .bias_set_combo = mtk_pinconf_bias_set_combo,
91 .bias_get_combo = mtk_pinconf_bias_get_combo,
92 .drive_set = mtk_pinconf_drive_set_rev1,
93 @@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
94 .ies_present = false,
95 .base_names = mt7986_pinctrl_register_base_names,
96 .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
97 + .pull_type = mt7986_pull_type,
98 .bias_set_combo = mtk_pinconf_bias_set_combo,
99 .bias_get_combo = mtk_pinconf_bias_get_combo,
100 .drive_set = mtk_pinconf_drive_set_rev1,
Kevin D-Bs staging tree