47b2455ae63fb94a3c6ffd738989367a988d64d1
[openwrt/staging/blogic.git] /
1 From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3 Date: Tue, 28 Feb 2023 15:45:18 +0100
4 Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often
10 have LEDs indicating state of selected USB ports. Describe those SoC USB
11 ports to allow using them as LED trigger sources.
12
13 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
14 Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/
15 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
16 ---
17 .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++
18 1 file changed, 39 insertions(+)
19
20 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
21 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
22 @@ -148,6 +148,19 @@
23 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
24 phys = <&usb_phy PHY_TYPE_USB2>;
25 status = "disabled";
26 +
27 + #address-cells = <1>;
28 + #size-cells = <0>;
29 +
30 + ehci_port1: port@1 {
31 + reg = <1>;
32 + #trigger-source-cells = <0>;
33 + };
34 +
35 + ehci_port2: port@2 {
36 + reg = <2>;
37 + #trigger-source-cells = <0>;
38 + };
39 };
40
41 ohci: usb@c400 {
42 @@ -156,6 +169,19 @@
43 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
44 phys = <&usb_phy PHY_TYPE_USB2>;
45 status = "disabled";
46 +
47 + #address-cells = <1>;
48 + #size-cells = <0>;
49 +
50 + ohci_port1: port@1 {
51 + reg = <1>;
52 + #trigger-source-cells = <0>;
53 + };
54 +
55 + ohci_port2: port@2 {
56 + reg = <2>;
57 + #trigger-source-cells = <0>;
58 + };
59 };
60
61 xhci: usb@d000 {
62 @@ -164,6 +190,19 @@
63 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
64 phys = <&usb_phy PHY_TYPE_USB3>;
65 status = "disabled";
66 +
67 + #address-cells = <1>;
68 + #size-cells = <0>;
69 +
70 + xhci_port1: port@1 {
71 + reg = <1>;
72 + #trigger-source-cells = <0>;
73 + };
74 +
75 + xhci_port2: port@2 {
76 + reg = <2>;
77 + #trigger-source-cells = <0>;
78 + };
79 };
80
81 bus@80000 {