git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From ee6adaada426e3f04925f93b4372fa3534889775 Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Thu, 12 May 2016 17:54:08 +0800
   4 Subject: [PATCH] MLK-12786-2: ASoC: fsl_sai: correct the clock source for
   5  mclk0
   6
   7 mclk0 is assigned through the device tree.
   8
   9 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  10 ---
  11  sound/soc/fsl/fsl_sai.c | 3 +--
  12  1 file changed, 1 insertion(+), 2 deletions(-)
  13
  14 --- a/sound/soc/fsl/fsl_sai.c
  15 +++ b/sound/soc/fsl/fsl_sai.c
  16 @@ -868,8 +868,7 @@ static int fsl_sai_probe(struct platform
  17                 sai->bus_clk = NULL;
  18         }
  19
  20 -       sai->mclk_clk[0] = sai->bus_clk;
  21 -       for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
  22 +       for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
  23                 sprintf(tmp, "mclk%d", i);
  24                 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
  25                 if (IS_ERR(sai->mclk_clk[i])) {