1 From 63c33bbfeb6842a956a0eb12901e28eb335bdb18 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Fri, 14 May 2021 23:00:07 +0200
4 Subject: [PATCH] net: dsa: qca8k: clear MASTER_EN after phy read/write
6 Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write
7 operation. The MDIO_MASTER_EN bit is not reset after read/write
8 operation and the next operation can be wrongly interpreted by the
9 switch as a mdio operation. This cause a production of wrong/garbage
10 data from the switch and underfined bheavior. (random port drop,
11 unplugged port flagged with link up, wrong port speed)
12 Also on driver remove the MASTER_CTRL can be left set and cause the
13 malfunction of any next driver using the mdio device.
15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
16 Signed-off-by: David S. Miller <davem@davemloft.net>
18 drivers/net/dsa/qca8k.c | 14 ++++++++++++--
19 1 file changed, 12 insertions(+), 2 deletions(-)
21 --- a/drivers/net/dsa/qca8k.c
22 +++ b/drivers/net/dsa/qca8k.c
23 @@ -649,8 +649,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
27 - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
28 - QCA8K_MDIO_MASTER_BUSY);
29 + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
30 + QCA8K_MDIO_MASTER_BUSY);
32 + /* even if the busy_wait timeouts try to clear the MASTER_EN */
33 + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
34 + QCA8K_MDIO_MASTER_EN);
40 @@ -685,6 +691,10 @@ qca8k_mdio_read(struct qca8k_priv *priv,
42 val &= QCA8K_MDIO_MASTER_DATA_MASK;
44 + /* even if the busy_wait timeouts try to clear the MASTER_EN */
45 + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
46 + QCA8K_MDIO_MASTER_EN);