git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From 9f7c0728efb0036f6f197126aa62da40cdf4713a Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Wed, 28 Apr 2021 16:14:21 +0100
   4 Subject: [PATCH] drm/vc4: Allow DBLCLK modes even if horz timing is
   5  odd.
   6
   7 The 2711 pixel valve can't produce odd horizontal timings, and
   8 checks were added to vc4_hdmi_encoder_atomic_check and
   9 vc4_hdmi_encoder_mode_valid to filter out/block selection of
  10 such modes.
  11
  12 Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing
  13 values before programming them into the PV. The PV values,
  14 therefore, can not be odd, and so the modes can be supported.
  15
  16 Amend the filtering appropriately.
  17
  18 See https://github.com/raspberrypi/linux/issues/4307
  19
  20 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  21 ---
  22  drivers/gpu/drm/vc4/vc4_hdmi.c | 2 ++
  23  1 file changed, 2 insertions(+)
  24
  25 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  26 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  27 @@ -1066,6 +1066,7 @@ static int vc4_hdmi_encoder_atomic_check
  28         unsigned long long tmds_rate;
  29
  30         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
  31 +           !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
  32             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
  33              (mode->hsync_end % 2) || (mode->htotal % 2)))
  34                 return -EINVAL;
  35 @@ -1110,6 +1111,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
  36         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
  37
  38         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
  39 +           !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
  40             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
  41              (mode->hsync_end % 2) || (mode->htotal % 2)))
  42                 return MODE_H_ILLEGAL;