git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From ab1ddb241bc1cb3d80aa51207810edd5cb0bbdc5 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Fri, 1 Mar 2024 12:43:03 +0200
   4 Subject: [PATCH 25/30] net: dsa: mt7530: put initialising PCS devices code
   5  back to original order
   6 MIME-Version: 1.0
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   8 Content-Transfer-Encoding: 8bit
   9
  10 The commit fae463084032 ("net: dsa: mt753x: fix pcs conversion regression")
  11 fixes regression caused by cpu_port_config manually calling phylink
  12 operations. cpu_port_config was deemed useless and was removed. Therefore,
  13 put initialising PCS devices code back to its original order.
  14
  15 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  16 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  17 ---
  18  drivers/net/dsa/mt7530.c | 20 ++++++++++----------
  19  1 file changed, 10 insertions(+), 10 deletions(-)
  20
  21 --- a/drivers/net/dsa/mt7530.c
  22 +++ b/drivers/net/dsa/mt7530.c
  23 @@ -2848,17 +2848,9 @@ static int
  24  mt753x_setup(struct dsa_switch *ds)
  25  {
  26         struct mt7530_priv *priv = ds->priv;
  27 -       int i, ret;
  28 +       int ret = priv->info->sw_setup(ds);
  29 +       int i;
  30
  31 -       /* Initialise the PCS devices */
  32 -       for (i = 0; i < priv->ds->num_ports; i++) {
  33 -               priv->pcs[i].pcs.ops = priv->info->pcs_ops;
  34 -               priv->pcs[i].pcs.neg_mode = true;
  35 -               priv->pcs[i].priv = priv;
  36 -               priv->pcs[i].port = i;
  37 -       }
  38 -
  39 -       ret = priv->info->sw_setup(ds);
  40         if (ret)
  41                 return ret;
  42
  43 @@ -2870,6 +2862,14 @@ mt753x_setup(struct dsa_switch *ds)
  44         if (ret && priv->irq)
  45                 mt7530_free_irq_common(priv);
  46
  47 +       /* Initialise the PCS devices */
  48 +       for (i = 0; i < priv->ds->num_ports; i++) {
  49 +               priv->pcs[i].pcs.ops = priv->info->pcs_ops;
  50 +               priv->pcs[i].pcs.neg_mode = true;
  51 +               priv->pcs[i].priv = priv;
  52 +               priv->pcs[i].port = i;
  53 +       }
  54 +
  55         if (priv->create_sgmii) {
  56                 ret = priv->create_sgmii(priv);
  57                 if (ret && priv->irq)