projects / openwrt / staging / chunkeey.git / blob
? search:


42deb82ea33b199a3457368e7c652e46b36f4e37
[openwrt/staging/chunkeey.git] /
1 From d05cf625f27335320a2ad883b7f7c4cd638dca99 Mon Sep 17 00:00:00 2001
2 From: Yuantian Tang <andy.tang@nxp.com>
3 Date: Mon, 5 Nov 2018 17:25:32 +0800
4 Subject: [PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support
5
6 Ls208xa has several thermal sensors. Add all the sensor id to dts
7 to enable them.
8
9 To make the dts cleaner, re-organize the nodes to split out the
10 common part so that it can be shared with other SoCs.
11
12 Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
13 ---
14 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 8 +-
15 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 8 +-
16 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 70 ++++---
17 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi | 99 ++++++++++
18 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi | 99 ++++++++++
19 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi | 99 ++++++++++
20 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi | 251 ++++++++++++++++++++++++
21 7 files changed, 590 insertions(+), 44 deletions(-)
22 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
23 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
24 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
25 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
26
27 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
28 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
29 @@ -12,7 +12,7 @@
30 #include "fsl-ls208xa.dtsi"
31
32 &cpu {
33 - cpu0: cpu@0 {
34 + cooling_map0: cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a57";
37 reg = <0x0>;
38 @@ -32,7 +32,7 @@
39 #cooling-cells = <2>;
40 };
41
42 - cpu2: cpu@100 {
43 + cooling_map1: cpu2: cpu@100 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a57";
46 reg = <0x100>;
47 @@ -52,7 +52,7 @@
48 #cooling-cells = <2>;
49 };
50
51 - cpu4: cpu@200 {
52 + cooling_map2: cpu4: cpu@200 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a57";
55 reg = <0x200>;
56 @@ -72,7 +72,7 @@
57 #cooling-cells = <2>;
58 };
59
60 - cpu6: cpu@300 {
61 + cooling_map3: cpu6: cpu@300 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a57";
64 reg = <0x300>;
65 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
66 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
67 @@ -12,7 +12,7 @@
68 #include "fsl-ls208xa.dtsi"
69
70 &cpu {
71 - cpu0: cpu@0 {
72 + cooling_map0: cpu0: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a72";
75 reg = <0x0>;
76 @@ -32,7 +32,7 @@
77 #cooling-cells = <2>;
78 };
79
80 - cpu2: cpu@100 {
81 + cooling_map1: cpu2: cpu@100 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a72";
84 reg = <0x100>;
85 @@ -52,7 +52,7 @@
86 #cooling-cells = <2>;
87 };
88
89 - cpu4: cpu@200 {
90 + cooling_map2: cpu4: cpu@200 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a72";
93 reg = <0x200>;
94 @@ -72,7 +72,7 @@
95 #cooling-cells = <2>;
96 };
97
98 - cpu6: cpu@300 {
99 + cooling_map3: cpu6: cpu@300 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a72";
102 reg = <0x300>;
103 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
104 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
105 @@ -77,42 +77,7 @@
106 mask = <0x2>;
107 };
108
109 - thermal-zones {
110 - cpu_thermal: cpu-thermal {
111 - polling-delay-passive = <1000>;
112 - polling-delay = <5000>;
113 -
114 - thermal-sensors = <&tmu 4>;
115 -
116 - trips {
117 - cpu_alert: cpu-alert {
118 - temperature = <75000>;
119 - hysteresis = <2000>;
120 - type = "passive";
121 - };
122 - cpu_crit: cpu-crit {
123 - temperature = <85000>;
124 - hysteresis = <2000>;
125 - type = "critical";
126 - };
127 - };
128 -
129 - cooling-maps {
130 - map0 {
131 - trip = <&cpu_alert>;
132 - cooling-device =
133 - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
134 - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
135 - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
136 - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
137 - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
138 - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
139 - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
140 - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 - };
142 - };
143 - };
144 - };
145 + #include "fsl-tmu.dtsi"
146
147 timer: timer {
148 compatible = "arm,armv8-timer";
149 @@ -907,3 +872,36 @@
150 };
151 };
152 };
153 +
154 +#include "fsl-tmu-map1.dtsi"
155 +#include "fsl-tmu-map2.dtsi"
156 +#include "fsl-tmu-map3.dtsi"
157 +&thermal_zones {
158 + thermal-zone1 {
159 + status = "okay";
160 + };
161 +
162 + thermal-zone2{
163 + status = "okay";
164 + };
165 +
166 + thermal-zone3{
167 + status = "okay";
168 + };
169 +
170 + thermal-zone4{
171 + status = "okay";
172 + };
173 +
174 + thermal-zone5{
175 + status = "okay";
176 + };
177 +
178 + thermal-zone6{
179 + status = "okay";
180 + };
181 +
182 + thermal-zone7 {
183 + status = "okay";
184 + };
185 +};
186 --- /dev/null
187 +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
188 @@ -0,0 +1,99 @@
189 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
190 +/*
191 + * Device Tree Include file for Thermal Monitor Unit.
192 + *
193 + * Copyright 2018 NXP
194 + *
195 + * Tang Yuantian <andy.tang@nxp.com>
196 + *
197 + */
198 +
199 +&thermal_zones {
200 + thermal-zone0 {
201 + cooling-maps {
202 + map1 {
203 + trip = <&alert0>;
204 + cooling-device =
205 + <&cooling_map1 THERMAL_NO_LIMIT
206 + THERMAL_NO_LIMIT>;
207 + };
208 + };
209 + };
210 +
211 + thermal-zone1 {
212 + cooling-maps {
213 + map1 {
214 + trip = <&alert1>;
215 + cooling-device =
216 + <&cooling_map1 THERMAL_NO_LIMIT
217 + THERMAL_NO_LIMIT>;
218 + };
219 + };
220 + };
221 +
222 + thermal-zone2 {
223 + cooling-maps {
224 + map1 {
225 + trip = <&alert2>;
226 + cooling-device =
227 + <&cooling_map1 THERMAL_NO_LIMIT
228 + THERMAL_NO_LIMIT>;
229 + };
230 + };
231 + };
232 +
233 + thermal-zone3 {
234 + cooling-maps {
235 + map1 {
236 + trip = <&alert3>;
237 + cooling-device =
238 + <&cooling_map1 THERMAL_NO_LIMIT
239 + THERMAL_NO_LIMIT>;
240 + };
241 + };
242 + };
243 +
244 + thermal-zone4 {
245 + cooling-maps {
246 + map1 {
247 + trip = <&alert4>;
248 + cooling-device =
249 + <&cooling_map1 THERMAL_NO_LIMIT
250 + THERMAL_NO_LIMIT>;
251 + };
252 + };
253 + };
254 +
255 + thermal-zone5 {
256 + cooling-maps {
257 + map1 {
258 + trip = <&alert5>;
259 + cooling-device =
260 + <&cooling_map1 THERMAL_NO_LIMIT
261 + THERMAL_NO_LIMIT>;
262 + };
263 + };
264 + };
265 +
266 + thermal-zone6 {
267 + cooling-maps {
268 + map1 {
269 + trip = <&alert6>;
270 + cooling-device =
271 + <&cooling_map1 THERMAL_NO_LIMIT
272 + THERMAL_NO_LIMIT>;
273 + };
274 + };
275 + };
276 +
277 + thermal-zone7 {
278 + cooling-maps {
279 + map1 {
280 + trip = <&alert7>;
281 + cooling-device =
282 + <&cooling_map1 THERMAL_NO_LIMIT
283 + THERMAL_NO_LIMIT>;
284 + };
285 + };
286 + };
287 +};
288 --- /dev/null
289 +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
290 @@ -0,0 +1,99 @@
291 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
292 +/*
293 + * Device Tree Include file for Thermal Monitor Unit.
294 + *
295 + * Copyright 2018 NXP
296 + *
297 + * Tang Yuantian <andy.tang@nxp.com>
298 + *
299 + */
300 +
301 +&thermal_zones {
302 + thermal-zone0 {
303 + cooling-maps {
304 + map2 {
305 + trip = <&alert0>;
306 + cooling-device =
307 + <&cooling_map2 THERMAL_NO_LIMIT
308 + THERMAL_NO_LIMIT>;
309 + };
310 + };
311 + };
312 +
313 + thermal-zone1 {
314 + cooling-maps {
315 + map2 {
316 + trip = <&alert1>;
317 + cooling-device =
318 + <&cooling_map2 THERMAL_NO_LIMIT
319 + THERMAL_NO_LIMIT>;
320 + };
321 + };
322 + };
323 +
324 + thermal-zone2 {
325 + cooling-maps {
326 + map2 {
327 + trip = <&alert2>;
328 + cooling-device =
329 + <&cooling_map2 THERMAL_NO_LIMIT
330 + THERMAL_NO_LIMIT>;
331 + };
332 + };
333 + };
334 +
335 + thermal-zone3 {
336 + cooling-maps {
337 + map2 {
338 + trip = <&alert3>;
339 + cooling-device =
340 + <&cooling_map2 THERMAL_NO_LIMIT
341 + THERMAL_NO_LIMIT>;
342 + };
343 + };
344 + };
345 +
346 + thermal-zone4 {
347 + cooling-maps {
348 + map2 {
349 + trip = <&alert4>;
350 + cooling-device =
351 + <&cooling_map2 THERMAL_NO_LIMIT
352 + THERMAL_NO_LIMIT>;
353 + };
354 + };
355 + };
356 +
357 + thermal-zone5 {
358 + cooling-maps {
359 + map2 {
360 + trip = <&alert5>;
361 + cooling-device =
362 + <&cooling_map2 THERMAL_NO_LIMIT
363 + THERMAL_NO_LIMIT>;
364 + };
365 + };
366 + };
367 +
368 + thermal-zone6 {
369 + cooling-maps {
370 + map2 {
371 + trip = <&alert6>;
372 + cooling-device =
373 + <&cooling_map2 THERMAL_NO_LIMIT
374 + THERMAL_NO_LIMIT>;
375 + };
376 + };
377 + };
378 +
379 + thermal-zone7 {
380 + cooling-maps {
381 + map2 {
382 + trip = <&alert7>;
383 + cooling-device =
384 + <&cooling_map2 THERMAL_NO_LIMIT
385 + THERMAL_NO_LIMIT>;
386 + };
387 + };
388 + };
389 +};
390 --- /dev/null
391 +++ b/arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
392 @@ -0,0 +1,99 @@
393 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
394 +/*
395 + * Device Tree Include file for Thermal Monitor Unit.
396 + *
397 + * Copyright 2018 NXP
398 + *
399 + * Tang Yuantian <andy.tang@nxp.com>
400 + *
401 + */
402 +
403 +&thermal_zones {
404 + thermal-zone0 {
405 + cooling-maps {
406 + map3 {
407 + trip = <&alert0>;
408 + cooling-device =
409 + <&cooling_map3 THERMAL_NO_LIMIT
410 + THERMAL_NO_LIMIT>;
411 + };
412 + };
413 + };
414 +
415 + thermal-zone1 {
416 + cooling-maps {
417 + map3 {
418 + trip = <&alert1>;
419 + cooling-device =
420 + <&cooling_map3 THERMAL_NO_LIMIT
421 + THERMAL_NO_LIMIT>;
422 + };
423 + };
424 + };
425 +
426 + thermal-zone2 {
427 + cooling-maps {
428 + map3 {
429 + trip = <&alert2>;
430 + cooling-device =
431 + <&cooling_map3 THERMAL_NO_LIMIT
432 + THERMAL_NO_LIMIT>;
433 + };
434 + };
435 + };
436 +
437 + thermal-zone3 {
438 + cooling-maps {
439 + map3 {
440 + trip = <&alert3>;
441 + cooling-device =
442 + <&cooling_map3 THERMAL_NO_LIMIT
443 + THERMAL_NO_LIMIT>;
444 + };
445 + };
446 + };
447 +
448 + thermal-zone4 {
449 + cooling-maps {
450 + map3 {
451 + trip = <&alert4>;
452 + cooling-device =
453 + <&cooling_map3 THERMAL_NO_LIMIT
454 + THERMAL_NO_LIMIT>;
455 + };
456 + };
457 + };
458 +
459 + thermal-zone5 {
460 + cooling-maps {
461 + map3 {
462 + trip = <&alert5>;
463 + cooling-device =
464 + <&cooling_map3 THERMAL_NO_LIMIT
465 + THERMAL_NO_LIMIT>;
466 + };
467 + };
468 + };
469 +
470 + thermal-zone6 {
471 + cooling-maps {
472 + map3 {
473 + trip = <&alert6>;
474 + cooling-device =
475 + <&cooling_map3 THERMAL_NO_LIMIT
476 + THERMAL_NO_LIMIT>;
477 + };
478 + };
479 + };
480 +
481 + thermal-zone7 {
482 + cooling-maps {
483 + map3 {
484 + trip = <&alert7>;
485 + cooling-device =
486 + <&cooling_map3 THERMAL_NO_LIMIT
487 + THERMAL_NO_LIMIT>;
488 + };
489 + };
490 + };
491 +};
492 --- /dev/null
493 +++ b/arch/arm64/boot/dts/freescale/fsl-tmu.dtsi
494 @@ -0,0 +1,251 @@
495 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
496 +/*
497 + * Device Tree Include file for Thermal Monitor Unit.
498 + *
499 + * Copyright 2018 NXP
500 + *
501 + * Tang Yuantian <andy.tang@nxp.com>
502 + *
503 + */
504 +
505 +thermal_zones: thermal-zones {
506 + thermal_zone0: thermal-zone0 {
507 + polling-delay-passive = <1000>;
508 + polling-delay = <5000>;
509 + thermal-sensors = <&tmu 0>;
510 + status = "disabled";
511 +
512 + trips {
513 + alert0: alert0 {
514 + temperature = <75000>;
515 + hysteresis = <2000>;
516 + type = "passive";
517 + };
518 +
519 + crit0: crit0 {
520 + temperature = <85000>;
521 + hysteresis = <2000>;
522 + type = "critical";
523 + };
524 + };
525 +
526 + cooling-maps {
527 + map0 {
528 + trip = <&alert0>;
529 + cooling-device =
530 + <&cooling_map0 THERMAL_NO_LIMIT
531 + THERMAL_NO_LIMIT>;
532 + };
533 + };
534 + };
535 +
536 + thermal-zone1 {
537 + polling-delay-passive = <1000>;
538 + polling-delay = <5000>;
539 + thermal-sensors = <&tmu 1>;
540 + status = "disabled";
541 +
542 + trips {
543 + alert1: alert1 {
544 + temperature = <75000>;
545 + hysteresis = <2000>;
546 + type = "passive";
547 + };
548 +
549 + crit1: crit1 {
550 + temperature = <85000>;
551 + hysteresis = <2000>;
552 + type = "critical";
553 + };
554 + };
555 +
556 + cooling-maps {
557 + map0 {
558 + trip = <&alert1>;
559 + cooling-device =
560 + <&cooling_map0 THERMAL_NO_LIMIT
561 + THERMAL_NO_LIMIT>;
562 + };
563 + };
564 + };
565 +
566 + thermal-zone2 {
567 + polling-delay-passive = <1000>;
568 + polling-delay = <5000>;
569 + thermal-sensors = <&tmu 2>;
570 + status = "disabled";
571 +
572 + trips {
573 + alert2: alert2 {
574 + temperature = <75000>;
575 + hysteresis = <2000>;
576 + type = "passive";
577 + };
578 +
579 + crit2: crit2 {
580 + temperature = <85000>;
581 + hysteresis = <2000>;
582 + type = "critical";
583 + };
584 + };
585 +
586 + cooling-maps {
587 + map0 {
588 + trip = <&alert2>;
589 + cooling-device =
590 + <&cooling_map0 THERMAL_NO_LIMIT
591 + THERMAL_NO_LIMIT>;
592 + };
593 + };
594 + };
595 +
596 + thermal-zone3 {
597 + polling-delay-passive = <1000>;
598 + polling-delay = <5000>;
599 + thermal-sensors = <&tmu 3>;
600 + status = "disabled";
601 +
602 + trips {
603 + alert3: alert3 {
604 + temperature = <75000>;
605 + hysteresis = <2000>;
606 + type = "passive";
607 + };
608 +
609 + crit3: crit3 {
610 + temperature = <85000>;
611 + hysteresis = <2000>;
612 + type = "critical";
613 + };
614 + };
615 +
616 + cooling-maps {
617 + map0 {
618 + trip = <&alert3>;
619 + cooling-device =
620 + <&cooling_map0 THERMAL_NO_LIMIT
621 + THERMAL_NO_LIMIT>;
622 + };
623 + };
624 + };
625 +
626 + thermal-zone4 {
627 + polling-delay-passive = <1000>;
628 + polling-delay = <5000>;
629 + thermal-sensors = <&tmu 4>;
630 + status = "disabled";
631 +
632 + trips {
633 + alert4: alert4 {
634 + temperature = <75000>;
635 + hysteresis = <2000>;
636 + type = "passive";
637 + };
638 +
639 + crit4: crit4 {
640 + temperature = <85000>;
641 + hysteresis = <2000>;
642 + type = "critical";
643 + };
644 + };
645 +
646 + cooling-maps {
647 + map0 {
648 + trip = <&alert4>;
649 + cooling-device =
650 + <&cooling_map0 THERMAL_NO_LIMIT
651 + THERMAL_NO_LIMIT>;
652 + };
653 + };
654 + };
655 +
656 + thermal-zone5 {
657 + polling-delay-passive = <1000>;
658 + polling-delay = <5000>;
659 + thermal-sensors = <&tmu 5>;
660 + status = "disabled";
661 +
662 + trips {
663 + alert5: alert5 {
664 + temperature = <75000>;
665 + hysteresis = <2000>;
666 + type = "passive";
667 + };
668 +
669 + crit5: crit5 {
670 + temperature = <85000>;
671 + hysteresis = <2000>;
672 + type = "critical";
673 + };
674 + };
675 +
676 + cooling-maps {
677 + map0 {
678 + trip = <&alert5>;
679 + cooling-device =
680 + <&cooling_map0 THERMAL_NO_LIMIT
681 + THERMAL_NO_LIMIT>;
682 + };
683 + };
684 + };
685 +
686 + thermal-zone6 {
687 + polling-delay-passive = <1000>;
688 + polling-delay = <5000>;
689 + thermal-sensors = <&tmu 6>;
690 + status = "disabled";
691 +
692 + trips {
693 + alert6: alert6 {
694 + temperature = <75000>;
695 + hysteresis = <2000>;
696 + type = "passive";
697 + };
698 +
699 + crit6: crit6 {
700 + temperature = <85000>;
701 + hysteresis = <2000>;
702 + type = "critical";
703 + };
704 + };
705 +
706 + cooling-maps {
707 + map0 {
708 + trip = <&alert6>;
709 + cooling-device =
710 + <&cooling_map0 THERMAL_NO_LIMIT
711 + THERMAL_NO_LIMIT>;
712 + };
713 + };
714 + };
715 +
716 + thermal-zone7 {
717 + polling-delay-passive = <1000>;
718 + polling-delay = <5000>;
719 + thermal-sensors = <&tmu 7>;
720 + status = "disabled";
721 +
722 + trips {
723 + alert7: alert7 {
724 + temperature = <75000>;
725 + hysteresis = <2000>;
726 + type = "passive";
727 + };
728 +
729 + crit7: crit7 {
730 + temperature = <85000>;
731 + hysteresis = <2000>;
732 + type = "critical";
733 + };
734 + };
735 +
736 + cooling-maps {
737 + map0 {
738 + trip = <&alert7>;
739 + cooling-device =
740 + <&cooling_map0 THERMAL_NO_LIMIT
741 + THERMAL_NO_LIMIT>;
742 + };
743 + };
744 + };
745 +};
Staging tree of Christian Lamparter