git.openwrt.org Git - openwrt/staging/hauke.git/blob

   1 From 7b126c5fbddf179c7d2c2393100329aa45cd8ac4 Mon Sep 17 00:00:00 2001
   2 From: Fugang Duan <fugang.duan@nxp.com>
   3 Date: Fri, 9 Aug 2019 15:14:08 +0800
   4 Subject: [PATCH] dmaengine: fsl-edma: calculate the real count for slave sg
   5
   6 Calculate the rela count for current slave sg after eDMA stop.
   7
   8 Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
   9 ---
  10  drivers/dma/fsl-edma-common.c | 11 ++++++++++-
  11  drivers/dma/fsl-edma-common.h |  2 ++
  12  drivers/dma/fsl-edma.c        |  1 +
  13  3 files changed, 13 insertions(+), 1 deletion(-)
  14
  15 --- a/drivers/dma/fsl-edma-common.c
  16 +++ b/drivers/dma/fsl-edma-common.c
  17 @@ -305,6 +305,11 @@ static size_t fsl_edma_desc_residue(stru
  18         return len;
  19  }
  20
  21 +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan)
  22 +{
  23 +       fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true);
  24 +}
  25 +
  26  enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
  27                 dma_cookie_t cookie, struct dma_tx_state *txstate)
  28  {
  29 @@ -314,8 +319,12 @@ enum dma_status fsl_edma_tx_status(struc
  30         unsigned long flags;
  31
  32         status = dma_cookie_status(chan, cookie, txstate);
  33 -       if (status == DMA_COMPLETE)
  34 +       if (status == DMA_COMPLETE) {
  35 +               spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
  36 +               txstate->residue = fsl_chan->chn_real_count;
  37 +               spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
  38                 return status;
  39 +       }
  40
  41         if (!txstate)
  42                 return fsl_chan->status;
  43 --- a/drivers/dma/fsl-edma-common.h
  44 +++ b/drivers/dma/fsl-edma-common.h
  45 @@ -126,6 +126,7 @@ struct fsl_edma_chan {
  46         u32                             dma_dev_size;
  47         enum dma_data_direction         dma_dir;
  48         char                            chan_name[16];
  49 +       u32                             chn_real_count;
  50  };
  51
  52  struct fsl_edma_desc {
  53 @@ -229,6 +230,7 @@ int fsl_edma_pause(struct dma_chan *chan
  54  int fsl_edma_resume(struct dma_chan *chan);
  55  int fsl_edma_slave_config(struct dma_chan *chan,
  56                                  struct dma_slave_config *cfg);
  57 +void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan);
  58  enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
  59                 dma_cookie_t cookie, struct dma_tx_state *txstate);
  60  struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
  61 --- a/drivers/dma/fsl-edma.c
  62 +++ b/drivers/dma/fsl-edma.c
  63 @@ -46,6 +46,7 @@ static irqreturn_t fsl_edma_tx_handler(i
  64
  65                         spin_lock(&fsl_chan->vchan.lock);
  66                         if (!fsl_chan->edesc->iscyclic) {
  67 +                               fsl_edma_get_realcnt(fsl_chan);
  68                                 list_del(&fsl_chan->edesc->vdesc.node);
  69                                 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
  70                                 fsl_chan->edesc = NULL;