git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 33239152305567b3e9bf052f71fd4baecd626341 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Tue, 10 Sep 2024 06:40:22 +0200
   4 Subject: [PATCH 1/3] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
   5
   6 Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
   7 set some peripherals that has this clock as their parent. When this driver
   8 was mainlined we could not find any active users of this SoC so we cannot
   9 perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
  10 device which uses this SoC appear and reported some issues in openWRT:
  11 - https://github.com/openwrt/openwrt/issues/16054
  12 The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
  13 has a not defined 'periph' clock as parent. Hence, introduce it to have a
  14 properly working clock plan for this SoC.
  15
  16 Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
  17 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  18 Link: https://lore.kernel.org/r/20240910044024.120009-2-sergio.paracuellos@gmail.com
  19 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  20 ---
  21  drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
  22  1 file changed, 7 insertions(+), 2 deletions(-)
  23
  24 --- a/drivers/clk/ralink/clk-mtmips.c
  25 +++ b/drivers/clk/ralink/clk-mtmips.c
  26 @@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fi
  27         CLK_FIXED("xtal", NULL, 40000000)
  28  };
  29
  30 +static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
  31 +       CLK_FIXED("xtal", NULL, 40000000),
  32 +       CLK_FIXED("periph", "xtal", 40000000)
  33 +};
  34 +
  35  static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
  36         CLK_FIXED("periph", "xtal", 40000000)
  37  };
  38 @@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt33
  39  static const struct mtmips_clk_data rt3883_clk_data = {
  40         .clk_base = rt3883_clks_base,
  41         .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
  42 -       .clk_fixed = rt305x_fixed_clocks,
  43 -       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
  44 +       .clk_fixed = rt3883_fixed_clocks,
  45 +       .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
  46         .clk_factor = NULL,
  47         .num_clk_factor = 0,
  48         .clk_periph = rt5350_pherip_clks,