git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From 33826e9c6ba76b265d4e26cb95493fa27ed78974 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Wed, 29 Dec 2021 11:23:14 +0100
   4 Subject: [PATCH] arm64: dts: broadcom: bcm4908: use proper TWD binding
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Block at <ff800400 0x4c> is a TWD that contains timers, watchdog and
  10 reset. Actual timers happen to be at block beginning but they only span
  11 across the first 0x28 registers. It means the old block description was
  12 incorrect (size 0x3c).
  13
  14 Drop timers binding for now and use documented TWD binding. Timers
  15 should be properly documented and defined as TWD subnode.
  16
  17 Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
  18 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  19 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  20 ---
  21  arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++----
  22  1 file changed, 4 insertions(+), 4 deletions(-)
  23
  24 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
  25 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
  26 @@ -273,9 +273,9 @@
  27                 #size-cells = <1>;
  28                 ranges = <0x00 0x00 0xff800000 0x3000>;
  29
  30 -               timer: timer@400 {
  31 -                       compatible = "brcm,bcm6328-timer", "syscon";
  32 -                       reg = <0x400 0x3c>;
  33 +               twd: timer-mfd@400 {
  34 +                       compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
  35 +                       reg = <0x400 0x4c>;
  36                 };
  37
  38                 gpio0: gpio-controller@500 {
  39 @@ -330,7 +330,7 @@
  40
  41         reboot {
  42                 compatible = "syscon-reboot";
  43 -               regmap = <&timer>;
  44 +               regmap = <&twd>;
  45                 offset = <0x34>;
  46                 mask = <1>;
  47         };