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1 From 01e67fe435419efedf2431d582fdd17340041453 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Mon, 21 Nov 2022 17:04:31 +0100
4 Subject: [PATCH] drm/vc4: tests: Fail the current test if we access a
5 register
6
7 Accessing a register when running under kunit is a bad idea since our
8 device is completely mocked.
9
10 Fail the current test if we ever access any of our hardware registers.
11
12 Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
13 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
14 ---
15 drivers/gpu/drm/vc4/vc4_crtc.c | 13 +++++++++++--
16 drivers/gpu/drm/vc4/vc4_dpi.c | 13 +++++++++++--
17 drivers/gpu/drm/vc4/vc4_drv.h | 29 +++++++++++++++++++++++++----
18 drivers/gpu/drm/vc4/vc4_dsi.c | 9 ++++++++-
19 drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 4 ++++
20 drivers/gpu/drm/vc4/vc4_txp.c | 13 +++++++++++--
21 drivers/gpu/drm/vc4/vc4_vec.c | 13 +++++++++++--
22 7 files changed, 81 insertions(+), 13 deletions(-)
23
24 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
25 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
26 @@ -50,8 +50,17 @@
27
28 #define HVS_FIFO_LATENCY_PIX 6
29
30 -#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
31 -#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
32 +#define CRTC_WRITE(offset, val) \
33 + do { \
34 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
35 + writel(val, vc4_crtc->regs + (offset)); \
36 + } while (0)
37 +
38 +#define CRTC_READ(offset) \
39 + ({ \
40 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
41 + readl(vc4_crtc->regs + (offset)); \
42 + })
43
44 static const struct debugfs_reg32 crtc_regs[] = {
45 VC4_REG32(PV_CONTROL),
46 --- a/drivers/gpu/drm/vc4/vc4_dpi.c
47 +++ b/drivers/gpu/drm/vc4/vc4_dpi.c
48 @@ -103,8 +103,17 @@ to_vc4_dpi(struct drm_encoder *encoder)
49 return container_of(encoder, struct vc4_dpi, encoder.base);
50 }
51
52 -#define DPI_READ(offset) readl(dpi->regs + (offset))
53 -#define DPI_WRITE(offset, val) writel(val, dpi->regs + (offset))
54 +#define DPI_READ(offset) \
55 + ({ \
56 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
57 + readl(dpi->regs + (offset)); \
58 + })
59 +
60 +#define DPI_WRITE(offset, val) \
61 + do { \
62 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
63 + writel(val, dpi->regs + (offset)); \
64 + } while (0)
65
66 static const struct debugfs_reg32 dpi_regs[] = {
67 VC4_REG32(DPI_C),
68 --- a/drivers/gpu/drm/vc4/vc4_drv.h
69 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
70 @@ -19,6 +19,8 @@
71 #include <drm/drm_mm.h>
72 #include <drm/drm_modeset_lock.h>
73
74 +#include <kunit/test-bug.h>
75 +
76 #include "uapi/drm/vc4_drm.h"
77 #include "vc4_regs.h"
78
79 @@ -669,10 +671,29 @@ to_vc4_crtc_state(const struct drm_crtc_
80 return container_of(crtc_state, struct vc4_crtc_state, base);
81 }
82
83 -#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
84 -#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
85 -#define HVS_READ(offset) readl(hvs->regs + offset)
86 -#define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
87 +#define V3D_READ(offset) \
88 + ({ \
89 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
90 + readl(vc4->v3d->regs + (offset)); \
91 + })
92 +
93 +#define V3D_WRITE(offset, val) \
94 + do { \
95 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
96 + writel(val, vc4->v3d->regs + (offset)); \
97 + } while (0)
98 +
99 +#define HVS_READ(offset) \
100 + ({ \
101 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
102 + readl(hvs->regs + (offset)); \
103 + })
104 +
105 +#define HVS_WRITE(offset, val) \
106 + do { \
107 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
108 + writel(val, hvs->regs + (offset)); \
109 + } while (0)
110
111 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
112
113 --- a/drivers/gpu/drm/vc4/vc4_dsi.c
114 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
115 @@ -623,6 +623,8 @@ dsi_dma_workaround_write(struct vc4_dsi
116 dma_cookie_t cookie;
117 int ret;
118
119 + kunit_fail_current_test("Accessing a register in a unit test!\n");
120 +
121 /* DSI0 should be able to write normally. */
122 if (!chan) {
123 writel(val, dsi->regs + offset);
124 @@ -651,7 +653,12 @@ dsi_dma_workaround_write(struct vc4_dsi
125 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
126 }
127
128 -#define DSI_READ(offset) readl(dsi->regs + (offset))
129 +#define DSI_READ(offset) \
130 + ({ \
131 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
132 + readl(dsi->regs + (offset)); \
133 + })
134 +
135 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
136 #define DSI_PORT_READ(offset) \
137 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
138 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
139 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
140 @@ -456,6 +456,8 @@ static inline u32 vc4_hdmi_read(struct v
141
142 WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
143
144 + kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
145 +
146 if (reg >= variant->num_registers) {
147 dev_warn(&hdmi->pdev->dev,
148 "Invalid register ID %u\n", reg);
149 @@ -486,6 +488,8 @@ static inline void vc4_hdmi_write(struct
150
151 WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
152
153 + kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
154 +
155 if (reg >= variant->num_registers) {
156 dev_warn(&hdmi->pdev->dev,
157 "Invalid register ID %u\n", reg);
158 --- a/drivers/gpu/drm/vc4/vc4_txp.c
159 +++ b/drivers/gpu/drm/vc4/vc4_txp.c
160 @@ -145,8 +145,17 @@
161 /* Number of lines received and committed to memory. */
162 #define TXP_PROGRESS 0x10
163
164 -#define TXP_READ(offset) readl(txp->regs + (offset))
165 -#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
166 +#define TXP_READ(offset) \
167 + ({ \
168 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
169 + readl(txp->regs + (offset)); \
170 + })
171 +
172 +#define TXP_WRITE(offset, val) \
173 + do { \
174 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
175 + writel(val, txp->regs + (offset)); \
176 + } while (0)
177
178 struct vc4_txp {
179 struct vc4_crtc base;
180 --- a/drivers/gpu/drm/vc4/vc4_vec.c
181 +++ b/drivers/gpu/drm/vc4/vc4_vec.c
182 @@ -207,8 +207,17 @@ struct vc4_vec {
183 struct debugfs_regset32 regset;
184 };
185
186 -#define VEC_READ(offset) readl(vec->regs + (offset))
187 -#define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
188 +#define VEC_READ(offset) \
189 + ({ \
190 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
191 + readl(vec->regs + (offset)); \
192 + })
193 +
194 +#define VEC_WRITE(offset, val) \
195 + do { \
196 + kunit_fail_current_test("Accessing a register in a unit test!\n"); \
197 + writel(val, vec->regs + (offset)); \
198 + } while (0)
199
200 static inline struct vc4_vec *
201 encoder_to_vc4_vec(struct drm_encoder *encoder)
Staging tree of Matthias Schiffer