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1 From 9d61d138ab30bbfe4a8609853c81e881c4054a0b Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3 Date: Thu, 11 Feb 2021 13:12:34 +0100
4 Subject: [PATCH] net: broadcom: rename BCM4908 driver & update DT binding
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 compatible string was updated to match normal naming convention so
10 update driver as well
11
12 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
13 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
14 Signed-off-by: David S. Miller <davem@davemloft.net>
15 ---
16 MAINTAINERS | 2 +-
17 drivers/net/ethernet/broadcom/Kconfig | 2 +-
18 drivers/net/ethernet/broadcom/Makefile | 2 +-
19 .../{bcm4908enet.c => bcm4908_enet.c} | 215 +++++++++---------
20 .../{bcm4908enet.h => bcm4908_enet.h} | 4 +-
21 5 files changed, 113 insertions(+), 112 deletions(-)
22 rename drivers/net/ethernet/broadcom/{bcm4908enet.c => bcm4908_enet.c} (68%)
23 rename drivers/net/ethernet/broadcom/{bcm4908enet.h => bcm4908_enet.h} (98%)
24
25 --- a/MAINTAINERS
26 +++ b/MAINTAINERS
27 @@ -3433,7 +3433,7 @@ M: bcm-kernel-feedback-list@broadcom.com
28 L: netdev@vger.kernel.org
29 S: Maintained
30 F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
31 -F: drivers/net/ethernet/broadcom/bcm4908enet.*
32 +F: drivers/net/ethernet/broadcom/bcm4908_enet.*
33 F: drivers/net/ethernet/broadcom/unimac.h
34
35 BROADCOM BCM5301X ARM ARCHITECTURE
36 --- a/drivers/net/ethernet/broadcom/Kconfig
37 +++ b/drivers/net/ethernet/broadcom/Kconfig
38 @@ -51,7 +51,7 @@ config B44_PCI
39 depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT
40 default y
41
42 -config BCM4908ENET
43 +config BCM4908_ENET
44 tristate "Broadcom BCM4908 internal mac support"
45 depends on ARCH_BCM4908 || COMPILE_TEST
46 default y
47 --- a/drivers/net/ethernet/broadcom/Makefile
48 +++ b/drivers/net/ethernet/broadcom/Makefile
49 @@ -4,7 +4,7 @@
50 #
51
52 obj-$(CONFIG_B44) += b44.o
53 -obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o
54 +obj-$(CONFIG_BCM4908_ENET) += bcm4908_enet.o
55 obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
56 obj-$(CONFIG_BCMGENET) += genet/
57 obj-$(CONFIG_BNX2) += bnx2.o
58 --- a/drivers/net/ethernet/broadcom/bcm4908enet.c
59 +++ /dev/null
60 @@ -1,676 +0,0 @@
61 -// SPDX-License-Identifier: GPL-2.0-only
62 -/*
63 - * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
64 - */
65 -
66 -#include <linux/delay.h>
67 -#include <linux/etherdevice.h>
68 -#include <linux/interrupt.h>
69 -#include <linux/module.h>
70 -#include <linux/of.h>
71 -#include <linux/platform_device.h>
72 -#include <linux/slab.h>
73 -#include <linux/string.h>
74 -
75 -#include "bcm4908enet.h"
76 -#include "unimac.h"
77 -
78 -#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
79 -#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
80 -#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
81 -#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
82 -
83 -#define ENET_TX_BDS_NUM 200
84 -#define ENET_RX_BDS_NUM 200
85 -#define ENET_RX_BDS_NUM_MAX 8192
86 -
87 -#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
88 - ENET_DMA_CH_CFG_INT_NO_DESC | \
89 - ENET_DMA_CH_CFG_INT_BUFF_DONE)
90 -#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
91 -
92 -#define ENET_MTU_MIN 60
93 -#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
94 -#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
95 -
96 -struct bcm4908enet_dma_ring_bd {
97 - __le32 ctl;
98 - __le32 addr;
99 -} __packed;
100 -
101 -struct bcm4908enet_dma_ring_slot {
102 - struct sk_buff *skb;
103 - unsigned int len;
104 - dma_addr_t dma_addr;
105 -};
106 -
107 -struct bcm4908enet_dma_ring {
108 - int is_tx;
109 - int read_idx;
110 - int write_idx;
111 - int length;
112 - u16 cfg_block;
113 - u16 st_ram_block;
114 -
115 - union {
116 - void *cpu_addr;
117 - struct bcm4908enet_dma_ring_bd *buf_desc;
118 - };
119 - dma_addr_t dma_addr;
120 -
121 - struct bcm4908enet_dma_ring_slot *slots;
122 -};
123 -
124 -struct bcm4908enet {
125 - struct device *dev;
126 - struct net_device *netdev;
127 - struct napi_struct napi;
128 - void __iomem *base;
129 -
130 - struct bcm4908enet_dma_ring tx_ring;
131 - struct bcm4908enet_dma_ring rx_ring;
132 -};
133 -
134 -/***
135 - * R/W ops
136 - */
137 -
138 -static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)
139 -{
140 - return readl(enet->base + offset);
141 -}
142 -
143 -static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)
144 -{
145 - writel(value, enet->base + offset);
146 -}
147 -
148 -static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
149 -{
150 - u32 val;
151 -
152 - WARN_ON(set & ~mask);
153 -
154 - val = enet_read(enet, offset);
155 - val = (val & ~mask) | (set & mask);
156 - enet_write(enet, offset, val);
157 -}
158 -
159 -static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)
160 -{
161 - enet_maskset(enet, offset, set, set);
162 -}
163 -
164 -static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)
165 -{
166 - return enet_read(enet, ENET_UNIMAC + offset);
167 -}
168 -
169 -static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)
170 -{
171 - enet_write(enet, ENET_UNIMAC + offset, value);
172 -}
173 -
174 -static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)
175 -{
176 - enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
177 -}
178 -
179 -static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)
180 -{
181 - enet_set(enet, ENET_UNIMAC + offset, set);
182 -}
183 -
184 -/***
185 - * Helpers
186 - */
187 -
188 -static void bcm4908enet_intrs_on(struct bcm4908enet *enet)
189 -{
190 - enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
191 -}
192 -
193 -static void bcm4908enet_intrs_off(struct bcm4908enet *enet)
194 -{
195 - enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
196 -}
197 -
198 -static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)
199 -{
200 - enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
201 -}
202 -
203 -/***
204 - * DMA
205 - */
206 -
207 -static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)
208 -{
209 - int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
210 - struct device *dev = enet->dev;
211 -
212 - ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
213 - if (!ring->cpu_addr)
214 - return -ENOMEM;
215 -
216 - if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
217 - dev_err(dev, "Invalid DMA ring alignment\n");
218 - goto err_free_buf_descs;
219 - }
220 -
221 - ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
222 - if (!ring->slots)
223 - goto err_free_buf_descs;
224 -
225 - memset(ring->cpu_addr, 0, size);
226 -
227 - ring->read_idx = 0;
228 - ring->write_idx = 0;
229 -
230 - return 0;
231 -
232 -err_free_buf_descs:
233 - dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
234 - return -ENOMEM;
235 -}
236 -
237 -static void bcm4908enet_dma_free(struct bcm4908enet *enet)
238 -{
239 - struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
240 - struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
241 - struct device *dev = enet->dev;
242 - int size;
243 -
244 - size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
245 - if (rx_ring->cpu_addr)
246 - dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
247 - kfree(rx_ring->slots);
248 -
249 - size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);
250 - if (tx_ring->cpu_addr)
251 - dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
252 - kfree(tx_ring->slots);
253 -}
254 -
255 -static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)
256 -{
257 - struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;
258 - struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
259 - struct device *dev = enet->dev;
260 - int err;
261 -
262 - tx_ring->length = ENET_TX_BDS_NUM;
263 - tx_ring->is_tx = 1;
264 - tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
265 - tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
266 - err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
267 - if (err) {
268 - dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
269 - return err;
270 - }
271 -
272 - rx_ring->length = ENET_RX_BDS_NUM;
273 - rx_ring->is_tx = 0;
274 - rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
275 - rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
276 - err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
277 - if (err) {
278 - dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
279 - bcm4908enet_dma_free(enet);
280 - return err;
281 - }
282 -
283 - return 0;
284 -}
285 -
286 -static void bcm4908enet_dma_reset(struct bcm4908enet *enet)
287 -{
288 - struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
289 - int i;
290 -
291 - /* Disable the DMA controller and channel */
292 - for (i = 0; i < ARRAY_SIZE(rings); i++)
293 - enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
294 - enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
295 -
296 - /* Reset channels state */
297 - for (i = 0; i < ARRAY_SIZE(rings); i++) {
298 - struct bcm4908enet_dma_ring *ring = rings[i];
299 -
300 - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
301 - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
302 - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
303 - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
304 - }
305 -}
306 -
307 -static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)
308 -{
309 - struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
310 - struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
311 - struct device *dev = enet->dev;
312 - u32 tmp;
313 - int err;
314 -
315 - slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
316 -
317 - slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
318 - if (!slot->skb)
319 - return -ENOMEM;
320 -
321 - slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
322 - err = dma_mapping_error(dev, slot->dma_addr);
323 - if (err) {
324 - dev_err(dev, "Failed to map DMA buffer: %d\n", err);
325 - kfree_skb(slot->skb);
326 - slot->skb = NULL;
327 - return err;
328 - }
329 -
330 - tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
331 - tmp |= DMA_CTL_STATUS_OWN;
332 - if (idx == enet->rx_ring.length - 1)
333 - tmp |= DMA_CTL_STATUS_WRAP;
334 - buf_desc->ctl = cpu_to_le32(tmp);
335 - buf_desc->addr = cpu_to_le32(slot->dma_addr);
336 -
337 - return 0;
338 -}
339 -
340 -static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,
341 - struct bcm4908enet_dma_ring *ring)
342 -{
343 - int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
344 - int reset_subch = ring->is_tx ? 1 : 0;
345 -
346 - /* Reset the DMA channel */
347 - enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
348 - enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
349 -
350 - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
351 - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
352 - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
353 -
354 - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
355 - (uint32_t)ring->dma_addr);
356 -}
357 -
358 -static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)
359 -{
360 - struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
361 - struct bcm4908enet_dma_ring_slot *slot;
362 - struct device *dev = enet->dev;
363 - int i;
364 -
365 - for (i = rx_ring->length - 1; i >= 0; i--) {
366 - slot = &rx_ring->slots[i];
367 - if (!slot->skb)
368 - continue;
369 - dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
370 - kfree_skb(slot->skb);
371 - slot->skb = NULL;
372 - }
373 -}
374 -
375 -static int bcm4908enet_dma_init(struct bcm4908enet *enet)
376 -{
377 - struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;
378 - struct device *dev = enet->dev;
379 - int err;
380 - int i;
381 -
382 - for (i = 0; i < rx_ring->length; i++) {
383 - err = bcm4908enet_dma_alloc_rx_buf(enet, i);
384 - if (err) {
385 - dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
386 - bcm4908enet_dma_uninit(enet);
387 - return err;
388 - }
389 - }
390 -
391 - bcm4908enet_dma_ring_init(enet, &enet->tx_ring);
392 - bcm4908enet_dma_ring_init(enet, &enet->rx_ring);
393 -
394 - return 0;
395 -}
396 -
397 -static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,
398 - struct bcm4908enet_dma_ring *ring)
399 -{
400 - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
401 -}
402 -
403 -static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,
404 - struct bcm4908enet_dma_ring *ring)
405 -{
406 - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
407 -}
408 -
409 -static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,
410 - struct bcm4908enet_dma_ring *ring)
411 -{
412 - enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
413 -}
414 -
415 -static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,
416 - struct bcm4908enet_dma_ring *ring)
417 -{
418 - unsigned long deadline;
419 - u32 tmp;
420 -
421 - enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
422 -
423 - deadline = jiffies + usecs_to_jiffies(2000);
424 - do {
425 - tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
426 - if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
427 - return;
428 - enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
429 - usleep_range(10, 30);
430 - } while (!time_after_eq(jiffies, deadline));
431 -
432 - dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
433 -}
434 -
435 -/***
436 - * Ethernet driver
437 - */
438 -
439 -static void bcm4908enet_gmac_init(struct bcm4908enet *enet)
440 -{
441 - u32 cmd;
442 -
443 - cmd = enet_umac_read(enet, UMAC_CMD);
444 - enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
445 - enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
446 -
447 - enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
448 - enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
449 -
450 - enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
451 - enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
452 -
453 - cmd = enet_umac_read(enet, UMAC_CMD);
454 - cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
455 - cmd &= ~CMD_TX_EN;
456 - cmd &= ~CMD_RX_EN;
457 - cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
458 - enet_umac_write(enet, UMAC_CMD, cmd);
459 -
460 - enet_maskset(enet, ENET_GMAC_STATUS,
461 - ENET_GMAC_STATUS_ETH_SPEED_MASK |
462 - ENET_GMAC_STATUS_HD |
463 - ENET_GMAC_STATUS_AUTO_CFG_EN |
464 - ENET_GMAC_STATUS_LINK_UP,
465 - ENET_GMAC_STATUS_ETH_SPEED_1000 |
466 - ENET_GMAC_STATUS_AUTO_CFG_EN |
467 - ENET_GMAC_STATUS_LINK_UP);
468 -}
469 -
470 -static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)
471 -{
472 - struct bcm4908enet *enet = dev_id;
473 -
474 - bcm4908enet_intrs_off(enet);
475 - bcm4908enet_intrs_ack(enet);
476 -
477 - napi_schedule(&enet->napi);
478 -
479 - return IRQ_HANDLED;
480 -}
481 -
482 -static int bcm4908enet_open(struct net_device *netdev)
483 -{
484 - struct bcm4908enet *enet = netdev_priv(netdev);
485 - struct device *dev = enet->dev;
486 - int err;
487 -
488 - err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet);
489 - if (err) {
490 - dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
491 - return err;
492 - }
493 -
494 - bcm4908enet_gmac_init(enet);
495 - bcm4908enet_dma_reset(enet);
496 - bcm4908enet_dma_init(enet);
497 -
498 - enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
499 -
500 - enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
501 - enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
502 - bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);
503 -
504 - napi_enable(&enet->napi);
505 - netif_carrier_on(netdev);
506 - netif_start_queue(netdev);
507 -
508 - bcm4908enet_intrs_ack(enet);
509 - bcm4908enet_intrs_on(enet);
510 -
511 - return 0;
512 -}
513 -
514 -static int bcm4908enet_stop(struct net_device *netdev)
515 -{
516 - struct bcm4908enet *enet = netdev_priv(netdev);
517 -
518 - netif_stop_queue(netdev);
519 - netif_carrier_off(netdev);
520 - napi_disable(&enet->napi);
521 -
522 - bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);
523 - bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);
524 -
525 - bcm4908enet_dma_uninit(enet);
526 -
527 - free_irq(enet->netdev->irq, enet);
528 -
529 - return 0;
530 -}
531 -
532 -static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
533 -{
534 - struct bcm4908enet *enet = netdev_priv(netdev);
535 - struct bcm4908enet_dma_ring *ring = &enet->tx_ring;
536 - struct bcm4908enet_dma_ring_slot *slot;
537 - struct device *dev = enet->dev;
538 - struct bcm4908enet_dma_ring_bd *buf_desc;
539 - int free_buf_descs;
540 - u32 tmp;
541 -
542 - /* Free transmitted skbs */
543 - while (ring->read_idx != ring->write_idx) {
544 - buf_desc = &ring->buf_desc[ring->read_idx];
545 - if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
546 - break;
547 - slot = &ring->slots[ring->read_idx];
548 -
549 - dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
550 - dev_kfree_skb(slot->skb);
551 - if (++ring->read_idx == ring->length)
552 - ring->read_idx = 0;
553 - }
554 -
555 - /* Don't use the last empty buf descriptor */
556 - if (ring->read_idx <= ring->write_idx)
557 - free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
558 - else
559 - free_buf_descs = ring->read_idx - ring->write_idx;
560 - if (free_buf_descs < 2)
561 - return NETDEV_TX_BUSY;
562 -
563 - /* Hardware removes OWN bit after sending data */
564 - buf_desc = &ring->buf_desc[ring->write_idx];
565 - if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
566 - netif_stop_queue(netdev);
567 - return NETDEV_TX_BUSY;
568 - }
569 -
570 - slot = &ring->slots[ring->write_idx];
571 - slot->skb = skb;
572 - slot->len = skb->len;
573 - slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
574 - if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
575 - return NETDEV_TX_BUSY;
576 -
577 - tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
578 - tmp |= DMA_CTL_STATUS_OWN;
579 - tmp |= DMA_CTL_STATUS_SOP;
580 - tmp |= DMA_CTL_STATUS_EOP;
581 - tmp |= DMA_CTL_STATUS_APPEND_CRC;
582 - if (ring->write_idx + 1 == ring->length - 1)
583 - tmp |= DMA_CTL_STATUS_WRAP;
584 -
585 - buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
586 - buf_desc->ctl = cpu_to_le32(tmp);
587 -
588 - bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
589 -
590 - if (++ring->write_idx == ring->length - 1)
591 - ring->write_idx = 0;
592 - enet->netdev->stats.tx_bytes += skb->len;
593 - enet->netdev->stats.tx_packets++;
594 -
595 - return NETDEV_TX_OK;
596 -}
597 -
598 -static int bcm4908enet_poll(struct napi_struct *napi, int weight)
599 -{
600 - struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);
601 - struct device *dev = enet->dev;
602 - int handled = 0;
603 -
604 - while (handled < weight) {
605 - struct bcm4908enet_dma_ring_bd *buf_desc;
606 - struct bcm4908enet_dma_ring_slot slot;
607 - u32 ctl;
608 - int len;
609 - int err;
610 -
611 - buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
612 - ctl = le32_to_cpu(buf_desc->ctl);
613 - if (ctl & DMA_CTL_STATUS_OWN)
614 - break;
615 -
616 - slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
617 -
618 - /* Provide new buffer before unpinning the old one */
619 - err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
620 - if (err)
621 - break;
622 -
623 - if (++enet->rx_ring.read_idx == enet->rx_ring.length)
624 - enet->rx_ring.read_idx = 0;
625 -
626 - len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
627 -
628 - if (len < ENET_MTU_MIN ||
629 - (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
630 - enet->netdev->stats.rx_dropped++;
631 - break;
632 - }
633 -
634 - dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
635 -
636 - skb_put(slot.skb, len - 4 + 2);
637 - slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
638 - netif_receive_skb(slot.skb);
639 -
640 - enet->netdev->stats.rx_packets++;
641 - enet->netdev->stats.rx_bytes += len;
642 - }
643 -
644 - if (handled < weight) {
645 - napi_complete_done(napi, handled);
646 - bcm4908enet_intrs_on(enet);
647 - }
648 -
649 - return handled;
650 -}
651 -
652 -static const struct net_device_ops bcm96xx_netdev_ops = {
653 - .ndo_open = bcm4908enet_open,
654 - .ndo_stop = bcm4908enet_stop,
655 - .ndo_start_xmit = bcm4908enet_start_xmit,
656 - .ndo_set_mac_address = eth_mac_addr,
657 -};
658 -
659 -static int bcm4908enet_probe(struct platform_device *pdev)
660 -{
661 - struct device *dev = &pdev->dev;
662 - struct net_device *netdev;
663 - struct bcm4908enet *enet;
664 - int err;
665 -
666 - netdev = devm_alloc_etherdev(dev, sizeof(*enet));
667 - if (!netdev)
668 - return -ENOMEM;
669 -
670 - enet = netdev_priv(netdev);
671 - enet->dev = dev;
672 - enet->netdev = netdev;
673 -
674 - enet->base = devm_platform_ioremap_resource(pdev, 0);
675 - if (IS_ERR(enet->base)) {
676 - dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
677 - return PTR_ERR(enet->base);
678 - }
679 -
680 - netdev->irq = platform_get_irq_byname(pdev, "rx");
681 - if (netdev->irq < 0)
682 - return netdev->irq;
683 -
684 - dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
685 -
686 - err = bcm4908enet_dma_alloc(enet);
687 - if (err)
688 - return err;
689 -
690 - SET_NETDEV_DEV(netdev, &pdev->dev);
691 - eth_hw_addr_random(netdev);
692 - netdev->netdev_ops = &bcm96xx_netdev_ops;
693 - netdev->min_mtu = ETH_ZLEN;
694 - netdev->mtu = ENET_MTU_MAX;
695 - netdev->max_mtu = ENET_MTU_MAX;
696 - netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);
697 -
698 - err = register_netdev(netdev);
699 - if (err) {
700 - bcm4908enet_dma_free(enet);
701 - return err;
702 - }
703 -
704 - platform_set_drvdata(pdev, enet);
705 -
706 - return 0;
707 -}
708 -
709 -static int bcm4908enet_remove(struct platform_device *pdev)
710 -{
711 - struct bcm4908enet *enet = platform_get_drvdata(pdev);
712 -
713 - unregister_netdev(enet->netdev);
714 - netif_napi_del(&enet->napi);
715 - bcm4908enet_dma_free(enet);
716 -
717 - return 0;
718 -}
719 -
720 -static const struct of_device_id bcm4908enet_of_match[] = {
721 - { .compatible = "brcm,bcm4908enet"},
722 - {},
723 -};
724 -
725 -static struct platform_driver bcm4908enet_driver = {
726 - .driver = {
727 - .name = "bcm4908enet",
728 - .of_match_table = bcm4908enet_of_match,
729 - },
730 - .probe = bcm4908enet_probe,
731 - .remove = bcm4908enet_remove,
732 -};
733 -module_platform_driver(bcm4908enet_driver);
734 -
735 -MODULE_LICENSE("GPL v2");
736 -MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);
737 --- /dev/null
738 +++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
739 @@ -0,0 +1,677 @@
740 +// SPDX-License-Identifier: GPL-2.0-only
741 +/*
742 + * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
743 + */
744 +
745 +#include <linux/delay.h>
746 +#include <linux/etherdevice.h>
747 +#include <linux/interrupt.h>
748 +#include <linux/module.h>
749 +#include <linux/of.h>
750 +#include <linux/platform_device.h>
751 +#include <linux/slab.h>
752 +#include <linux/string.h>
753 +
754 +#include "bcm4908_enet.h"
755 +#include "unimac.h"
756 +
757 +#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG
758 +#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG
759 +#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM
760 +#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM
761 +
762 +#define ENET_TX_BDS_NUM 200
763 +#define ENET_RX_BDS_NUM 200
764 +#define ENET_RX_BDS_NUM_MAX 8192
765 +
766 +#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \
767 + ENET_DMA_CH_CFG_INT_NO_DESC | \
768 + ENET_DMA_CH_CFG_INT_BUFF_DONE)
769 +#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */
770 +
771 +#define ENET_MTU_MIN 60
772 +#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */
773 +#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */
774 +
775 +struct bcm4908_enet_dma_ring_bd {
776 + __le32 ctl;
777 + __le32 addr;
778 +} __packed;
779 +
780 +struct bcm4908_enet_dma_ring_slot {
781 + struct sk_buff *skb;
782 + unsigned int len;
783 + dma_addr_t dma_addr;
784 +};
785 +
786 +struct bcm4908_enet_dma_ring {
787 + int is_tx;
788 + int read_idx;
789 + int write_idx;
790 + int length;
791 + u16 cfg_block;
792 + u16 st_ram_block;
793 +
794 + union {
795 + void *cpu_addr;
796 + struct bcm4908_enet_dma_ring_bd *buf_desc;
797 + };
798 + dma_addr_t dma_addr;
799 +
800 + struct bcm4908_enet_dma_ring_slot *slots;
801 +};
802 +
803 +struct bcm4908_enet {
804 + struct device *dev;
805 + struct net_device *netdev;
806 + struct napi_struct napi;
807 + void __iomem *base;
808 +
809 + struct bcm4908_enet_dma_ring tx_ring;
810 + struct bcm4908_enet_dma_ring rx_ring;
811 +};
812 +
813 +/***
814 + * R/W ops
815 + */
816 +
817 +static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset)
818 +{
819 + return readl(enet->base + offset);
820 +}
821 +
822 +static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)
823 +{
824 + writel(value, enet->base + offset);
825 +}
826 +
827 +static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
828 +{
829 + u32 val;
830 +
831 + WARN_ON(set & ~mask);
832 +
833 + val = enet_read(enet, offset);
834 + val = (val & ~mask) | (set & mask);
835 + enet_write(enet, offset, val);
836 +}
837 +
838 +static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)
839 +{
840 + enet_maskset(enet, offset, set, set);
841 +}
842 +
843 +static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)
844 +{
845 + return enet_read(enet, ENET_UNIMAC + offset);
846 +}
847 +
848 +static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)
849 +{
850 + enet_write(enet, ENET_UNIMAC + offset, value);
851 +}
852 +
853 +static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
854 +{
855 + enet_maskset(enet, ENET_UNIMAC + offset, mask, set);
856 +}
857 +
858 +static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)
859 +{
860 + enet_set(enet, ENET_UNIMAC + offset, set);
861 +}
862 +
863 +/***
864 + * Helpers
865 + */
866 +
867 +static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet)
868 +{
869 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
870 +}
871 +
872 +static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet)
873 +{
874 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);
875 +}
876 +
877 +static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet)
878 +{
879 + enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
880 +}
881 +
882 +/***
883 + * DMA
884 + */
885 +
886 +static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet,
887 + struct bcm4908_enet_dma_ring *ring)
888 +{
889 + int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
890 + struct device *dev = enet->dev;
891 +
892 + ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
893 + if (!ring->cpu_addr)
894 + return -ENOMEM;
895 +
896 + if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
897 + dev_err(dev, "Invalid DMA ring alignment\n");
898 + goto err_free_buf_descs;
899 + }
900 +
901 + ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);
902 + if (!ring->slots)
903 + goto err_free_buf_descs;
904 +
905 + memset(ring->cpu_addr, 0, size);
906 +
907 + ring->read_idx = 0;
908 + ring->write_idx = 0;
909 +
910 + return 0;
911 +
912 +err_free_buf_descs:
913 + dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
914 + return -ENOMEM;
915 +}
916 +
917 +static void bcm4908_enet_dma_free(struct bcm4908_enet *enet)
918 +{
919 + struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
920 + struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
921 + struct device *dev = enet->dev;
922 + int size;
923 +
924 + size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
925 + if (rx_ring->cpu_addr)
926 + dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
927 + kfree(rx_ring->slots);
928 +
929 + size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
930 + if (tx_ring->cpu_addr)
931 + dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
932 + kfree(tx_ring->slots);
933 +}
934 +
935 +static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet)
936 +{
937 + struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
938 + struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
939 + struct device *dev = enet->dev;
940 + int err;
941 +
942 + tx_ring->length = ENET_TX_BDS_NUM;
943 + tx_ring->is_tx = 1;
944 + tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
945 + tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
946 + err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
947 + if (err) {
948 + dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
949 + return err;
950 + }
951 +
952 + rx_ring->length = ENET_RX_BDS_NUM;
953 + rx_ring->is_tx = 0;
954 + rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
955 + rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
956 + err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
957 + if (err) {
958 + dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
959 + bcm4908_enet_dma_free(enet);
960 + return err;
961 + }
962 +
963 + return 0;
964 +}
965 +
966 +static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet)
967 +{
968 + struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
969 + int i;
970 +
971 + /* Disable the DMA controller and channel */
972 + for (i = 0; i < ARRAY_SIZE(rings); i++)
973 + enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
974 + enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
975 +
976 + /* Reset channels state */
977 + for (i = 0; i < ARRAY_SIZE(rings); i++) {
978 + struct bcm4908_enet_dma_ring *ring = rings[i];
979 +
980 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
981 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
982 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
983 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
984 + }
985 +}
986 +
987 +static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)
988 +{
989 + struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
990 + struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
991 + struct device *dev = enet->dev;
992 + u32 tmp;
993 + int err;
994 +
995 + slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;
996 +
997 + slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
998 + if (!slot->skb)
999 + return -ENOMEM;
1000 +
1001 + slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
1002 + err = dma_mapping_error(dev, slot->dma_addr);
1003 + if (err) {
1004 + dev_err(dev, "Failed to map DMA buffer: %d\n", err);
1005 + kfree_skb(slot->skb);
1006 + slot->skb = NULL;
1007 + return err;
1008 + }
1009 +
1010 + tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
1011 + tmp |= DMA_CTL_STATUS_OWN;
1012 + if (idx == enet->rx_ring.length - 1)
1013 + tmp |= DMA_CTL_STATUS_WRAP;
1014 + buf_desc->ctl = cpu_to_le32(tmp);
1015 + buf_desc->addr = cpu_to_le32(slot->dma_addr);
1016 +
1017 + return 0;
1018 +}
1019 +
1020 +static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet,
1021 + struct bcm4908_enet_dma_ring *ring)
1022 +{
1023 + int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
1024 + int reset_subch = ring->is_tx ? 1 : 0;
1025 +
1026 + /* Reset the DMA channel */
1027 + enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
1028 + enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
1029 +
1030 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
1031 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
1032 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
1033 +
1034 + enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
1035 + (uint32_t)ring->dma_addr);
1036 +}
1037 +
1038 +static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)
1039 +{
1040 + struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
1041 + struct bcm4908_enet_dma_ring_slot *slot;
1042 + struct device *dev = enet->dev;
1043 + int i;
1044 +
1045 + for (i = rx_ring->length - 1; i >= 0; i--) {
1046 + slot = &rx_ring->slots[i];
1047 + if (!slot->skb)
1048 + continue;
1049 + dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
1050 + kfree_skb(slot->skb);
1051 + slot->skb = NULL;
1052 + }
1053 +}
1054 +
1055 +static int bcm4908_enet_dma_init(struct bcm4908_enet *enet)
1056 +{
1057 + struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
1058 + struct device *dev = enet->dev;
1059 + int err;
1060 + int i;
1061 +
1062 + for (i = 0; i < rx_ring->length; i++) {
1063 + err = bcm4908_enet_dma_alloc_rx_buf(enet, i);
1064 + if (err) {
1065 + dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
1066 + bcm4908_enet_dma_uninit(enet);
1067 + return err;
1068 + }
1069 + }
1070 +
1071 + bcm4908_enet_dma_ring_init(enet, &enet->tx_ring);
1072 + bcm4908_enet_dma_ring_init(enet, &enet->rx_ring);
1073 +
1074 + return 0;
1075 +}
1076 +
1077 +static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet,
1078 + struct bcm4908_enet_dma_ring *ring)
1079 +{
1080 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
1081 +}
1082 +
1083 +static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet,
1084 + struct bcm4908_enet_dma_ring *ring)
1085 +{
1086 + enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
1087 +}
1088 +
1089 +static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet,
1090 + struct bcm4908_enet_dma_ring *ring)
1091 +{
1092 + enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
1093 +}
1094 +
1095 +static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet,
1096 + struct bcm4908_enet_dma_ring *ring)
1097 +{
1098 + unsigned long deadline;
1099 + u32 tmp;
1100 +
1101 + enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
1102 +
1103 + deadline = jiffies + usecs_to_jiffies(2000);
1104 + do {
1105 + tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
1106 + if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
1107 + return;
1108 + enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
1109 + usleep_range(10, 30);
1110 + } while (!time_after_eq(jiffies, deadline));
1111 +
1112 + dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
1113 +}
1114 +
1115 +/***
1116 + * Ethernet driver
1117 + */
1118 +
1119 +static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet)
1120 +{
1121 + u32 cmd;
1122 +
1123 + cmd = enet_umac_read(enet, UMAC_CMD);
1124 + enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
1125 + enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
1126 +
1127 + enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
1128 + enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
1129 +
1130 + enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
1131 + enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
1132 +
1133 + cmd = enet_umac_read(enet, UMAC_CMD);
1134 + cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
1135 + cmd &= ~CMD_TX_EN;
1136 + cmd &= ~CMD_RX_EN;
1137 + cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
1138 + enet_umac_write(enet, UMAC_CMD, cmd);
1139 +
1140 + enet_maskset(enet, ENET_GMAC_STATUS,
1141 + ENET_GMAC_STATUS_ETH_SPEED_MASK |
1142 + ENET_GMAC_STATUS_HD |
1143 + ENET_GMAC_STATUS_AUTO_CFG_EN |
1144 + ENET_GMAC_STATUS_LINK_UP,
1145 + ENET_GMAC_STATUS_ETH_SPEED_1000 |
1146 + ENET_GMAC_STATUS_AUTO_CFG_EN |
1147 + ENET_GMAC_STATUS_LINK_UP);
1148 +}
1149 +
1150 +static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)
1151 +{
1152 + struct bcm4908_enet *enet = dev_id;
1153 +
1154 + bcm4908_enet_intrs_off(enet);
1155 + bcm4908_enet_intrs_ack(enet);
1156 +
1157 + napi_schedule(&enet->napi);
1158 +
1159 + return IRQ_HANDLED;
1160 +}
1161 +
1162 +static int bcm4908_enet_open(struct net_device *netdev)
1163 +{
1164 + struct bcm4908_enet *enet = netdev_priv(netdev);
1165 + struct device *dev = enet->dev;
1166 + int err;
1167 +
1168 + err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet);
1169 + if (err) {
1170 + dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
1171 + return err;
1172 + }
1173 +
1174 + bcm4908_enet_gmac_init(enet);
1175 + bcm4908_enet_dma_reset(enet);
1176 + bcm4908_enet_dma_init(enet);
1177 +
1178 + enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
1179 +
1180 + enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
1181 + enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
1182 + bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);
1183 +
1184 + napi_enable(&enet->napi);
1185 + netif_carrier_on(netdev);
1186 + netif_start_queue(netdev);
1187 +
1188 + bcm4908_enet_intrs_ack(enet);
1189 + bcm4908_enet_intrs_on(enet);
1190 +
1191 + return 0;
1192 +}
1193 +
1194 +static int bcm4908_enet_stop(struct net_device *netdev)
1195 +{
1196 + struct bcm4908_enet *enet = netdev_priv(netdev);
1197 +
1198 + netif_stop_queue(netdev);
1199 + netif_carrier_off(netdev);
1200 + napi_disable(&enet->napi);
1201 +
1202 + bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
1203 + bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
1204 +
1205 + bcm4908_enet_dma_uninit(enet);
1206 +
1207 + free_irq(enet->netdev->irq, enet);
1208 +
1209 + return 0;
1210 +}
1211 +
1212 +static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1213 +{
1214 + struct bcm4908_enet *enet = netdev_priv(netdev);
1215 + struct bcm4908_enet_dma_ring *ring = &enet->tx_ring;
1216 + struct bcm4908_enet_dma_ring_slot *slot;
1217 + struct device *dev = enet->dev;
1218 + struct bcm4908_enet_dma_ring_bd *buf_desc;
1219 + int free_buf_descs;
1220 + u32 tmp;
1221 +
1222 + /* Free transmitted skbs */
1223 + while (ring->read_idx != ring->write_idx) {
1224 + buf_desc = &ring->buf_desc[ring->read_idx];
1225 + if (buf_desc->ctl & DMA_CTL_STATUS_OWN)
1226 + break;
1227 + slot = &ring->slots[ring->read_idx];
1228 +
1229 + dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
1230 + dev_kfree_skb(slot->skb);
1231 + if (++ring->read_idx == ring->length)
1232 + ring->read_idx = 0;
1233 + }
1234 +
1235 + /* Don't use the last empty buf descriptor */
1236 + if (ring->read_idx <= ring->write_idx)
1237 + free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
1238 + else
1239 + free_buf_descs = ring->read_idx - ring->write_idx;
1240 + if (free_buf_descs < 2)
1241 + return NETDEV_TX_BUSY;
1242 +
1243 + /* Hardware removes OWN bit after sending data */
1244 + buf_desc = &ring->buf_desc[ring->write_idx];
1245 + if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
1246 + netif_stop_queue(netdev);
1247 + return NETDEV_TX_BUSY;
1248 + }
1249 +
1250 + slot = &ring->slots[ring->write_idx];
1251 + slot->skb = skb;
1252 + slot->len = skb->len;
1253 + slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
1254 + if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
1255 + return NETDEV_TX_BUSY;
1256 +
1257 + tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
1258 + tmp |= DMA_CTL_STATUS_OWN;
1259 + tmp |= DMA_CTL_STATUS_SOP;
1260 + tmp |= DMA_CTL_STATUS_EOP;
1261 + tmp |= DMA_CTL_STATUS_APPEND_CRC;
1262 + if (ring->write_idx + 1 == ring->length - 1)
1263 + tmp |= DMA_CTL_STATUS_WRAP;
1264 +
1265 + buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
1266 + buf_desc->ctl = cpu_to_le32(tmp);
1267 +
1268 + bcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring);
1269 +
1270 + if (++ring->write_idx == ring->length - 1)
1271 + ring->write_idx = 0;
1272 + enet->netdev->stats.tx_bytes += skb->len;
1273 + enet->netdev->stats.tx_packets++;
1274 +
1275 + return NETDEV_TX_OK;
1276 +}
1277 +
1278 +static int bcm4908_enet_poll(struct napi_struct *napi, int weight)
1279 +{
1280 + struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi);
1281 + struct device *dev = enet->dev;
1282 + int handled = 0;
1283 +
1284 + while (handled < weight) {
1285 + struct bcm4908_enet_dma_ring_bd *buf_desc;
1286 + struct bcm4908_enet_dma_ring_slot slot;
1287 + u32 ctl;
1288 + int len;
1289 + int err;
1290 +
1291 + buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
1292 + ctl = le32_to_cpu(buf_desc->ctl);
1293 + if (ctl & DMA_CTL_STATUS_OWN)
1294 + break;
1295 +
1296 + slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
1297 +
1298 + /* Provide new buffer before unpinning the old one */
1299 + err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
1300 + if (err)
1301 + break;
1302 +
1303 + if (++enet->rx_ring.read_idx == enet->rx_ring.length)
1304 + enet->rx_ring.read_idx = 0;
1305 +
1306 + len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
1307 +
1308 + if (len < ENET_MTU_MIN ||
1309 + (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
1310 + enet->netdev->stats.rx_dropped++;
1311 + break;
1312 + }
1313 +
1314 + dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
1315 +
1316 + skb_put(slot.skb, len - 4 + 2);
1317 + slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
1318 + netif_receive_skb(slot.skb);
1319 +
1320 + enet->netdev->stats.rx_packets++;
1321 + enet->netdev->stats.rx_bytes += len;
1322 + }
1323 +
1324 + if (handled < weight) {
1325 + napi_complete_done(napi, handled);
1326 + bcm4908_enet_intrs_on(enet);
1327 + }
1328 +
1329 + return handled;
1330 +}
1331 +
1332 +static const struct net_device_ops bcm96xx_netdev_ops = {
1333 + .ndo_open = bcm4908_enet_open,
1334 + .ndo_stop = bcm4908_enet_stop,
1335 + .ndo_start_xmit = bcm4908_enet_start_xmit,
1336 + .ndo_set_mac_address = eth_mac_addr,
1337 +};
1338 +
1339 +static int bcm4908_enet_probe(struct platform_device *pdev)
1340 +{
1341 + struct device *dev = &pdev->dev;
1342 + struct net_device *netdev;
1343 + struct bcm4908_enet *enet;
1344 + int err;
1345 +
1346 + netdev = devm_alloc_etherdev(dev, sizeof(*enet));
1347 + if (!netdev)
1348 + return -ENOMEM;
1349 +
1350 + enet = netdev_priv(netdev);
1351 + enet->dev = dev;
1352 + enet->netdev = netdev;
1353 +
1354 + enet->base = devm_platform_ioremap_resource(pdev, 0);
1355 + if (IS_ERR(enet->base)) {
1356 + dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
1357 + return PTR_ERR(enet->base);
1358 + }
1359 +
1360 + netdev->irq = platform_get_irq_byname(pdev, "rx");
1361 + if (netdev->irq < 0)
1362 + return netdev->irq;
1363 +
1364 + dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
1365 +
1366 + err = bcm4908_enet_dma_alloc(enet);
1367 + if (err)
1368 + return err;
1369 +
1370 + SET_NETDEV_DEV(netdev, &pdev->dev);
1371 + eth_hw_addr_random(netdev);
1372 + netdev->netdev_ops = &bcm96xx_netdev_ops;
1373 + netdev->min_mtu = ETH_ZLEN;
1374 + netdev->mtu = ENET_MTU_MAX;
1375 + netdev->max_mtu = ENET_MTU_MAX;
1376 + netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);
1377 +
1378 + err = register_netdev(netdev);
1379 + if (err) {
1380 + bcm4908_enet_dma_free(enet);
1381 + return err;
1382 + }
1383 +
1384 + platform_set_drvdata(pdev, enet);
1385 +
1386 + return 0;
1387 +}
1388 +
1389 +static int bcm4908_enet_remove(struct platform_device *pdev)
1390 +{
1391 + struct bcm4908_enet *enet = platform_get_drvdata(pdev);
1392 +
1393 + unregister_netdev(enet->netdev);
1394 + netif_napi_del(&enet->napi);
1395 + bcm4908_enet_dma_free(enet);
1396 +
1397 + return 0;
1398 +}
1399 +
1400 +static const struct of_device_id bcm4908_enet_of_match[] = {
1401 + { .compatible = "brcm,bcm4908-enet"},
1402 + {},
1403 +};
1404 +
1405 +static struct platform_driver bcm4908_enet_driver = {
1406 + .driver = {
1407 + .name = "bcm4908_enet",
1408 + .of_match_table = bcm4908_enet_of_match,
1409 + },
1410 + .probe = bcm4908_enet_probe,
1411 + .remove = bcm4908_enet_remove,
1412 +};
1413 +module_platform_driver(bcm4908_enet_driver);
1414 +
1415 +MODULE_LICENSE("GPL v2");
1416 +MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match);
1417 --- a/drivers/net/ethernet/broadcom/bcm4908enet.h
1418 +++ /dev/null
1419 @@ -1,96 +0,0 @@
1420 -/* SPDX-License-Identifier: GPL-2.0-only */
1421 -#ifndef __BCM4908ENET_H
1422 -#define __BCM4908ENET_H
1423 -
1424 -#define ENET_CONTROL 0x000
1425 -#define ENET_MIB_CTRL 0x004
1426 -#define ENET_MIB_CTRL_CLR_MIB 0x00000001
1427 -#define ENET_RX_ERR_MASK 0x008
1428 -#define ENET_MIB_MAX_PKT_SIZE 0x00C
1429 -#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
1430 -#define ENET_DIAG_OUT 0x01c
1431 -#define ENET_ENABLE_DROP_PKT 0x020
1432 -#define ENET_IRQ_ENABLE 0x024
1433 -#define ENET_IRQ_ENABLE_OVFL 0x00000001
1434 -#define ENET_GMAC_STATUS 0x028
1435 -#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
1436 -#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
1437 -#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
1438 -#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
1439 -#define ENET_GMAC_STATUS_HD 0x00000004
1440 -#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
1441 -#define ENET_GMAC_STATUS_LINK_UP 0x00000010
1442 -#define ENET_IRQ_STATUS 0x02c
1443 -#define ENET_IRQ_STATUS_OVFL 0x00000001
1444 -#define ENET_OVERFLOW_COUNTER 0x030
1445 -#define ENET_FLUSH 0x034
1446 -#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
1447 -#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
1448 -#define ENET_RSV_SELECT 0x038
1449 -#define ENET_BP_FORCE 0x03c
1450 -#define ENET_BP_FORCE_FORCE 0x00000001
1451 -#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
1452 -#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
1453 -#define ENET_TX_CRC_CTRL 0x044
1454 -#define ENET_MIB 0x200
1455 -#define ENET_UNIMAC 0x400
1456 -#define ENET_DMA 0x800
1457 -#define ENET_DMA_CONTROLLER_CFG 0x800
1458 -#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
1459 -#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
1460 -#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
1461 -#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
1462 -#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
1463 -#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
1464 -#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
1465 -#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
1466 -#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
1467 -#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
1468 -#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
1469 -#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
1470 -#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
1471 -#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
1472 -#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
1473 -#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
1474 -#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
1475 -#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
1476 -#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
1477 -#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
1478 -#define ENET_DMA_CH0_CFG 0xa00 /* RX */
1479 -#define ENET_DMA_CH1_CFG 0xa10 /* TX */
1480 -#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
1481 -#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
1482 -
1483 -#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
1484 -#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
1485 -#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
1486 -#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
1487 -#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
1488 -#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
1489 -#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
1490 -#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
1491 -#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
1492 -#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
1493 -#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
1494 -#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
1495 -#define ENET_DMA_CH_CFG_SIZE 0x10
1496 -
1497 -#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
1498 -#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
1499 -#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
1500 -#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
1501 -#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
1502 -
1503 -#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
1504 -#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
1505 -#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
1506 -#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
1507 -#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
1508 -#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
1509 -#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
1510 -#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
1511 -#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
1512 -#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
1513 -#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
1514 -
1515 -#endif
1516 --- /dev/null
1517 +++ b/drivers/net/ethernet/broadcom/bcm4908_enet.h
1518 @@ -0,0 +1,96 @@
1519 +/* SPDX-License-Identifier: GPL-2.0-only */
1520 +#ifndef __BCM4908_ENET_H
1521 +#define __BCM4908_ENET_H
1522 +
1523 +#define ENET_CONTROL 0x000
1524 +#define ENET_MIB_CTRL 0x004
1525 +#define ENET_MIB_CTRL_CLR_MIB 0x00000001
1526 +#define ENET_RX_ERR_MASK 0x008
1527 +#define ENET_MIB_MAX_PKT_SIZE 0x00C
1528 +#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
1529 +#define ENET_DIAG_OUT 0x01c
1530 +#define ENET_ENABLE_DROP_PKT 0x020
1531 +#define ENET_IRQ_ENABLE 0x024
1532 +#define ENET_IRQ_ENABLE_OVFL 0x00000001
1533 +#define ENET_GMAC_STATUS 0x028
1534 +#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
1535 +#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
1536 +#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
1537 +#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
1538 +#define ENET_GMAC_STATUS_HD 0x00000004
1539 +#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
1540 +#define ENET_GMAC_STATUS_LINK_UP 0x00000010
1541 +#define ENET_IRQ_STATUS 0x02c
1542 +#define ENET_IRQ_STATUS_OVFL 0x00000001
1543 +#define ENET_OVERFLOW_COUNTER 0x030
1544 +#define ENET_FLUSH 0x034
1545 +#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
1546 +#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
1547 +#define ENET_RSV_SELECT 0x038
1548 +#define ENET_BP_FORCE 0x03c
1549 +#define ENET_BP_FORCE_FORCE 0x00000001
1550 +#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
1551 +#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
1552 +#define ENET_TX_CRC_CTRL 0x044
1553 +#define ENET_MIB 0x200
1554 +#define ENET_UNIMAC 0x400
1555 +#define ENET_DMA 0x800
1556 +#define ENET_DMA_CONTROLLER_CFG 0x800
1557 +#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
1558 +#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
1559 +#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
1560 +#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
1561 +#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
1562 +#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
1563 +#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
1564 +#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
1565 +#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
1566 +#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
1567 +#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
1568 +#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
1569 +#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
1570 +#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
1571 +#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
1572 +#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
1573 +#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
1574 +#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
1575 +#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
1576 +#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
1577 +#define ENET_DMA_CH0_CFG 0xa00 /* RX */
1578 +#define ENET_DMA_CH1_CFG 0xa10 /* TX */
1579 +#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
1580 +#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
1581 +
1582 +#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
1583 +#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
1584 +#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
1585 +#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
1586 +#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
1587 +#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
1588 +#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
1589 +#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
1590 +#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
1591 +#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
1592 +#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
1593 +#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
1594 +#define ENET_DMA_CH_CFG_SIZE 0x10
1595 +
1596 +#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
1597 +#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
1598 +#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
1599 +#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
1600 +#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
1601 +
1602 +#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
1603 +#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
1604 +#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
1605 +#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
1606 +#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
1607 +#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
1608 +#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
1609 +#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
1610 +#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
1611 +#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
1612 +#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
1613 +
1614 +#endif
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