3bb5e57c87a700876e79f16ca1aec9c44b729f32
[openwrt/staging/neocturne.git] /
1 From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sat, 26 Feb 2022 14:52:30 +0100
4 Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc
5 table
6
7 Add additional freq supported for the sdc table. The ops are changed to
8 the floor_ops to handle a freq request of 52kHz where we need to provide
9 a freq of 51.2kHz instead for stability reason.
10
11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
12 Reviewed-by: Stephen Boyd <sboyd@kernel.org>
13 Tested-by: Jonathan McDowell <noodles@earth.li>
14 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
15 Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com
16 ---
17 drivers/clk/qcom/gcc-ipq806x.c | 3 ++-
18 1 file changed, 2 insertions(+), 1 deletion(-)
19
20 --- a/drivers/clk/qcom/gcc-ipq806x.c
21 +++ b/drivers/clk/qcom/gcc-ipq806x.c
22 @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc
23 { 20210000, P_PLL8, 1, 1, 19 },
24 { 24000000, P_PLL8, 4, 1, 4 },
25 { 48000000, P_PLL8, 4, 1, 2 },
26 + { 51200000, P_PLL8, 1, 2, 15 },
27 { 64000000, P_PLL8, 3, 1, 2 },
28 { 96000000, P_PLL8, 4, 0, 0 },
29 { 192000000, P_PLL8, 2, 0, 0 },
30 @@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = {
31 .name = "sdc1_src",
32 .parent_data = gcc_pxo_pll8,
33 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
34 - .ops = &clk_rcg_ops,
35 + .ops = &clk_rcg_floor_ops,
36 },
37 }
38 };