git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 2a7fa96feddb63d36d64336a994dc4132e8a5cd4 Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@freescale.com>
   3 Date: Mon, 29 Dec 2014 13:40:08 +0800
   4 Subject: [PATCH] MLK-9974: ASoC: fsl_sai: There is underrun detected in the
   5  beginning sometimes
   6
   7 Write initial words to SAI FIFO to reduce underrun error
   8
   9 Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
  10 (cherry picked from commit 7ba8ae883d84540fac5ed4147d124399537bc0b3)
  11 (cherry picked from commit f4435f35aa2a97551d2c4a12ca316c354a880f85)
  12 ---
  13  sound/soc/fsl/fsl_sai.c | 7 +++++++
  14  1 file changed, 7 insertions(+)
  15
  16 --- a/sound/soc/fsl/fsl_sai.c
  17 +++ b/sound/soc/fsl/fsl_sai.c
  18 @@ -506,7 +506,9 @@ static int fsl_sai_trigger(struct snd_pc
  19  {
  20         struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
  21         bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  22 +       u8 channels = substream->runtime->channels;
  23         u32 xcsr, count = 100;
  24 +       int i;
  25
  26         /*
  27          * Asynchronous mode: Clear SYNC for both Tx and Rx.
  28 @@ -529,6 +531,11 @@ static int fsl_sai_trigger(struct snd_pc
  29                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
  30                                    FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
  31
  32 +               for (i = 0; tx && i < channels; i++)
  33 +                       regmap_write(sai->regmap, FSL_SAI_TDR, 0x0);
  34 +               if (tx)
  35 +                       udelay(10);
  36 +
  37                 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
  38                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
  39                 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,