projects / openwrt / staging / pepe2k.git / blob
? search:


39c2f178350bf19efa34e6bc3f9cb1ef41b2550b
[openwrt/staging/pepe2k.git] /
1 From 737c0c8d07b5f671c0a33cec95965fcb2d2ea893 Mon Sep 17 00:00:00 2001
2 From: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
3 Date: Sat, 24 Feb 2024 11:45:12 +0000
4 Subject: [PATCH] nvmem: zynqmp_nvmem: Add support to access efuse
5
6 Add support to read/write efuse memory map of ZynqMP.
7 Below are the offsets of ZynqMP efuse memory map
8 0 - SOC version(read only)
9 0xC - 0xFC -ZynqMP specific purpose efuses
10 0x100 - 0x17F - Physical Unclonable Function(PUF)
11 efuses repurposed as user efuses
12
13 Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
14 Acked-by: Kalyani Akula <Kalyani.akula@amd.com>
15 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 Link: https://lore.kernel.org/r/20240224114516.86365-8-srinivas.kandagatla@linaro.org
17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 ---
19 drivers/nvmem/zynqmp_nvmem.c | 186 +++++++++++++++++++++++++++++++++--
20 1 file changed, 176 insertions(+), 10 deletions(-)
21
22 --- a/drivers/nvmem/zynqmp_nvmem.c
23 +++ b/drivers/nvmem/zynqmp_nvmem.c
24 @@ -4,6 +4,7 @@
25 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
26 */
27
28 +#include <linux/dma-mapping.h>
29 #include <linux/module.h>
30 #include <linux/nvmem-provider.h>
31 #include <linux/of.h>
32 @@ -11,24 +12,189 @@
33 #include <linux/firmware/xlnx-zynqmp.h>
34
35 #define SILICON_REVISION_MASK 0xF
36 +#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
37 +#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
38 +#define WORD_INBYTES 4
39 +#define SOC_VER_SIZE 0x4
40 +#define EFUSE_MEMORY_SIZE 0x177
41 +#define UNUSED_SPACE 0x8
42 +#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
43 + EFUSE_MEMORY_SIZE)
44 +#define SOC_VERSION_OFFSET 0x0
45 +#define EFUSE_START_OFFSET 0xC
46 +#define EFUSE_END_OFFSET 0xFC
47 +#define EFUSE_PUF_START_OFFSET 0x100
48 +#define EFUSE_PUF_MID_OFFSET 0x140
49 +#define EFUSE_PUF_END_OFFSET 0x17F
50 +#define EFUSE_NOT_ENABLED 29
51
52 +/*
53 + * efuse access type
54 + */
55 +enum efuse_access {
56 + EFUSE_READ = 0,
57 + EFUSE_WRITE
58 +};
59 +
60 +/**
61 + * struct xilinx_efuse - the basic structure
62 + * @src: address of the buffer to store the data to be write/read
63 + * @size: read/write word count
64 + * @offset: read/write offset
65 + * @flag: 0 - represents efuse read and 1- represents efuse write
66 + * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
67 + * 1 - represents puf user fuse row number.
68 + *
69 + * this structure stores all the required details to
70 + * read/write efuse memory.
71 + */
72 +struct xilinx_efuse {
73 + u64 src;
74 + u32 size;
75 + u32 offset;
76 + enum efuse_access flag;
77 + u32 pufuserfuse;
78 +};
79 +
80 +static int zynqmp_efuse_access(void *context, unsigned int offset,
81 + void *val, size_t bytes, enum efuse_access flag,
82 + unsigned int pufflag)
83 +{
84 + struct device *dev = context;
85 + struct xilinx_efuse *efuse;
86 + dma_addr_t dma_addr;
87 + dma_addr_t dma_buf;
88 + size_t words = bytes / WORD_INBYTES;
89 + int ret;
90 + int value;
91 + char *data;
92
93 -static int zynqmp_nvmem_read(void *context, unsigned int offset,
94 - void *val, size_t bytes)
95 + if (bytes % WORD_INBYTES != 0) {
96 + dev_err(dev, "Bytes requested should be word aligned\n");
97 + return -EOPNOTSUPP;
98 + }
99 +
100 + if (pufflag == 0 && offset % WORD_INBYTES) {
101 + dev_err(dev, "Offset requested should be word aligned\n");
102 + return -EOPNOTSUPP;
103 + }
104 +
105 + if (pufflag == 1 && flag == EFUSE_WRITE) {
106 + memcpy(&value, val, bytes);
107 + if ((offset == EFUSE_PUF_START_OFFSET ||
108 + offset == EFUSE_PUF_MID_OFFSET) &&
109 + value & P_USER_0_64_UPPER_MASK) {
110 + dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n");
111 + return -EOPNOTSUPP;
112 + }
113 +
114 + if (offset == EFUSE_PUF_END_OFFSET &&
115 + (value & P_USER_127_LOWER_4_BIT_MASK)) {
116 + dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n");
117 + return -EOPNOTSUPP;
118 + }
119 + }
120 +
121 + efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
122 + &dma_addr, GFP_KERNEL);
123 + if (!efuse)
124 + return -ENOMEM;
125 +
126 + data = dma_alloc_coherent(dev, sizeof(bytes),
127 + &dma_buf, GFP_KERNEL);
128 + if (!data) {
129 + ret = -ENOMEM;
130 + goto efuse_data_fail;
131 + }
132 +
133 + if (flag == EFUSE_WRITE) {
134 + memcpy(data, val, bytes);
135 + efuse->flag = EFUSE_WRITE;
136 + } else {
137 + efuse->flag = EFUSE_READ;
138 + }
139 +
140 + efuse->src = dma_buf;
141 + efuse->size = words;
142 + efuse->offset = offset;
143 + efuse->pufuserfuse = pufflag;
144 +
145 + zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
146 + if (ret != 0) {
147 + if (ret == EFUSE_NOT_ENABLED) {
148 + dev_err(dev, "efuse access is not enabled\n");
149 + ret = -EOPNOTSUPP;
150 + } else {
151 + dev_err(dev, "Error in efuse read %x\n", ret);
152 + ret = -EPERM;
153 + }
154 + goto efuse_access_err;
155 + }
156 +
157 + if (flag == EFUSE_READ)
158 + memcpy(val, data, bytes);
159 +efuse_access_err:
160 + dma_free_coherent(dev, sizeof(bytes),
161 + data, dma_buf);
162 +efuse_data_fail:
163 + dma_free_coherent(dev, sizeof(struct xilinx_efuse),
164 + efuse, dma_addr);
165 +
166 + return ret;
167 +}
168 +
169 +static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes)
170 {
171 struct device *dev = context;
172 int ret;
173 + int pufflag = 0;
174 int idcode;
175 int version;
176
177 - ret = zynqmp_pm_get_chipid(&idcode, &version);
178 - if (ret < 0)
179 - return ret;
180 + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
181 + pufflag = 1;
182 +
183 + switch (offset) {
184 + /* Soc version offset is zero */
185 + case SOC_VERSION_OFFSET:
186 + if (bytes != SOC_VER_SIZE)
187 + return -EOPNOTSUPP;
188 +
189 + ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version);
190 + if (ret < 0)
191 + return ret;
192 +
193 + dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
194 + *(int *)val = version & SILICON_REVISION_MASK;
195 + break;
196 + /* Efuse offset starts from 0xc */
197 + case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
198 + case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
199 + ret = zynqmp_efuse_access(context, offset, val,
200 + bytes, EFUSE_READ, pufflag);
201 + break;
202 + default:
203 + *(u32 *)val = 0xDEADBEEF;
204 + ret = 0;
205 + break;
206 + }
207 +
208 + return ret;
209 +}
210 +
211 +static int zynqmp_nvmem_write(void *context,
212 + unsigned int offset, void *val, size_t bytes)
213 +{
214 + int pufflag = 0;
215 +
216 + if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
217 + return -EOPNOTSUPP;
218
219 - dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
220 - *(int *)val = version & SILICON_REVISION_MASK;
221 + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
222 + pufflag = 1;
223
224 - return 0;
225 + return zynqmp_efuse_access(context, offset,
226 + val, bytes, EFUSE_WRITE, pufflag);
227 }
228
229 static const struct of_device_id zynqmp_nvmem_match[] = {
230 @@ -45,11 +211,11 @@ static int zynqmp_nvmem_probe(struct pla
231 econfig.name = "zynqmp-nvmem";
232 econfig.owner = THIS_MODULE;
233 econfig.word_size = 1;
234 - econfig.size = 1;
235 + econfig.size = ZYNQMP_NVMEM_SIZE;
236 econfig.dev = dev;
237 econfig.add_legacy_fixed_of_cells = true;
238 - econfig.read_only = true;
239 econfig.reg_read = zynqmp_nvmem_read;
240 + econfig.reg_write = zynqmp_nvmem_write;
241
242 return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
243 }
Staging tree of Piotr Dymacz