git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 5508bc9764760ca32990d5f7fa494be78e711ff6 Mon Sep 17 00:00:00 2001
   2 From: Li Yang <leoyang.li@nxp.com>
   3 Date: Fri, 5 Oct 2018 18:22:46 -0500
   4 Subject: [PATCH] arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDB
   5
   6 This patch add support for NXP LS2081ARDB board which has
   7 LS2081A SoC.
   8
   9 LS2081A SoC is 40-pin derivative of LS2088A SoC
  10 So, from functional perspective both are same.
  11 Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
  12
  13 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
  14 Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
  15 Signed-off-by: Tao Yang <b31903@freescale.com>
  16 Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
  17 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
  18 Signed-off-by: Li Yang <leoyang.li@nxp.com>
  19 ---
  20  arch/arm64/boot/dts/freescale/Makefile            |   1 +
  21  arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 127 ++++++++++++++++++++++
  22  2 files changed, 128 insertions(+)
  23  create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
  24
  25 --- a/arch/arm64/boot/dts/freescale/Makefile
  26 +++ b/arch/arm64/boot/dts/freescale/Makefile
  27 @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
  28  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
  29  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
  30  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
  31 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
  32  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
  33  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
  34  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
  35 --- /dev/null
  36 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
  37 @@ -0,0 +1,127 @@
  38 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  39 +/*
  40 + * Device Tree file for NXP LS2081A RDB Board.
  41 + *
  42 + * Copyright 2017 NXP
  43 + *
  44 + * Priyanka Jain <priyanka.jain@nxp.com>
  45 + *
  46 + */
  47 +
  48 +/dts-v1/;
  49 +
  50 +#include "fsl-ls2088a.dtsi"
  51 +
  52 +/ {
  53 +       model = "NXP Layerscape 2081A RDB Board";
  54 +       compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
  55 +
  56 +       aliases {
  57 +               serial0 = &serial0;
  58 +               serial1 = &serial1;
  59 +       };
  60 +
  61 +       chosen {
  62 +               stdout-path = "serial1:115200n8";
  63 +       };
  64 +};
  65 +
  66 +&esdhc {
  67 +       status = "okay";
  68 +};
  69 +
  70 +&ifc {
  71 +       status = "disabled";
  72 +};
  73 +
  74 +&i2c0 {
  75 +       status = "okay";
  76 +       pca9547@75 {
  77 +               compatible = "nxp,pca9547";
  78 +               reg = <0x75>;
  79 +               #address-cells = <1>;
  80 +               #size-cells = <0>;
  81 +               i2c@1 {
  82 +                       #address-cells = <1>;
  83 +                       #size-cells = <0>;
  84 +                       reg = <0x01>;
  85 +                       rtc@51 {
  86 +                               compatible = "nxp,pcf2129";
  87 +                               reg = <0x51>;
  88 +                       };
  89 +               };
  90 +
  91 +               i2c@2 {
  92 +                       #address-cells = <1>;
  93 +                       #size-cells = <0>;
  94 +                       reg = <0x02>;
  95 +
  96 +                       ina220@40 {
  97 +                               compatible = "ti,ina220";
  98 +                               reg = <0x40>;
  99 +                               shunt-resistor = <500>;
 100 +                       };
 101 +               };
 102 +
 103 +               i2c@3 {
 104 +                       #address-cells = <1>;
 105 +                       #size-cells = <0>;
 106 +                       reg = <0x3>;
 107 +
 108 +                       adt7481@4c {
 109 +                               compatible = "adi,adt7461";
 110 +                               reg = <0x4c>;
 111 +                       };
 112 +               };
 113 +       };
 114 +};
 115 +
 116 +&dspi {
 117 +       status = "okay";
 118 +       dflash0: n25q512a@0 {
 119 +               #address-cells = <1>;
 120 +               #size-cells = <1>;
 121 +               compatible = "st,m25p80";
 122 +               spi-max-frequency = <3000000>;
 123 +               reg = <0>;
 124 +       };
 125 +};
 126 +
 127 +&qspi {
 128 +       status = "okay";
 129 +       fsl,qspi-has-second-chip;
 130 +       flash0: s25fs512s@0 {
 131 +               #address-cells = <1>;
 132 +               #size-cells = <1>;
 133 +               compatible = "spansion,m25p80";
 134 +               spi-rx-bus-width = <4>;
 135 +               spi-tx-bus-width = <4>;
 136 +               spi-max-frequency = <20000000>;
 137 +               reg = <0>;
 138 +       };
 139 +       flash1: s25fs512s@1 {
 140 +               #address-cells = <1>;
 141 +               #size-cells = <1>;
 142 +               spi-rx-bus-width = <4>;
 143 +               spi-tx-bus-width = <4>;
 144 +               compatible = "spansion,m25p80";
 145 +               spi-max-frequency = <20000000>;
 146 +               reg = <1>;
 147 +       };
 148 +};
 149 +
 150 +&sata0 {
 151 +       status = "okay";
 152 +};
 153 +
 154 +&sata1 {
 155 +       status = "okay";
 156 +};
 157 +
 158 +&usb0 {
 159 +       status = "okay";
 160 +};
 161 +
 162 +&usb1 {
 163 +       status = "okay";
 164 +};