git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 29 Jul 2022 11:15:35 +0800
   4 Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver
   5
   6 This add CLK_XTAL macro and flag to mediatek clock driver common part,
   7 to make thi SoC that has clock directlly connect to XTAL working.
   8
   9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 ---
  11  drivers/clk/mediatek/clk-mtk.c | 4 ++++
  12  drivers/clk/mediatek/clk-mtk.h | 3 ++-
  13  2 files changed, 6 insertions(+), 1 deletion(-)
  14
  15 --- a/drivers/clk/mediatek/clk-mtk.c
  16 +++ b/drivers/clk/mediatek/clk-mtk.c
  17 @@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rat
  18                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
  19                 break;
  20
  21 +       case CLK_PARENT_XTAL:
  22         default:
  23                 rate = priv->tree->xtal_rate;
  24         }
  25 @@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rat
  26                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
  27                                                 priv->parent);
  28                 break;
  29 +       case CLK_PARENT_XTAL:
  30 +               rate = priv->tree->xtal_rate;
  31 +               break;
  32         default:
  33                 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
  34         }
  35 --- a/drivers/clk/mediatek/clk-mtk.h
  36 +++ b/drivers/clk/mediatek/clk-mtk.h
  37 @@ -29,7 +29,8 @@
  38  #define CLK_PARENT_APMIXED             BIT(4)
  39  #define CLK_PARENT_TOPCKGEN            BIT(5)
  40  #define CLK_PARENT_INFRASYS            BIT(6)
  41 -#define CLK_PARENT_MASK                        GENMASK(6, 4)
  42 +#define CLK_PARENT_XTAL                        BIT(7)
  43 +#define CLK_PARENT_MASK                        GENMASK(7, 4)
  44
  45  #define ETHSYS_HIFSYS_RST_CTRL_OFS     0x34
  46