git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From b2dd96ec88b7eb4288ca39a1fc78176872c0683b Mon Sep 17 00:00:00 2001
   2 From: Viorel Suman <viorel.suman@nxp.com>
   3 Date: Wed, 27 Jun 2018 10:59:12 +0300
   4 Subject: [PATCH] MLK-18682-2: ASoC: fsl: sai: allow dynamic pll switching
   5
   6 Currently SAI master clock derives from an audio pll that cannot be
   7 changed at runtime. iMX8 SoC has 2 audio plls usually configured to support
   8 either 8000Hz (8k,16k,32k,48k,etc) or 11025Hz (11k,22k,44.1k,88.2k,etc)
   9 ranges of rates - thus at runtime a SAI interface is able to play only one
  10 range of rates. The patch allows dynamic SAI master clock reparenting to
  11 the appropriate audio pll as function of the audio stream rate to be
  12 played/recorded.
  13
  14 Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
  15 ---
  16  sound/soc/fsl/fsl_sai.c | 60 ++++++++++++++++++++++++++++++++++++++++++++-----
  17  sound/soc/fsl/fsl_sai.h |  2 ++
  18  2 files changed, 57 insertions(+), 5 deletions(-)
  19
  20 --- a/sound/soc/fsl/fsl_sai.c
  21 +++ b/sound/soc/fsl/fsl_sai.c
  22 @@ -5,6 +5,7 @@
  23  // Copyright 2012-2016 Freescale Semiconductor, Inc.
  24
  25  #include <linux/clk.h>
  26 +#include <linux/clk-provider.h>
  27  #include <linux/delay.h>
  28  #include <linux/dmaengine.h>
  29  #include <linux/module.h>
  30 @@ -234,6 +235,50 @@ static int fsl_sai_set_dai_sysclk_tr(str
  31         return 0;
  32  }
  33
  34 +static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id,
  35 +               unsigned int freq)
  36 +{
  37 +       struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
  38 +       struct clk *p = sai->mclk_clk[clk_id], *pll = 0, *npll = 0;
  39 +       u64 ratio = freq;
  40 +       int ret;
  41 +
  42 +       while (p && sai->pll8k_clk && sai->pll11k_clk) {
  43 +               struct clk *pp = clk_get_parent(p);
  44 +
  45 +               if (clk_is_match(pp, sai->pll8k_clk) ||
  46 +                   clk_is_match(pp, sai->pll11k_clk)) {
  47 +                       pll = pp;
  48 +                       break;
  49 +               }
  50 +               p = pp;
  51 +       }
  52 +
  53 +       if (pll) {
  54 +               npll = (do_div(ratio, 8000) ? sai->pll11k_clk : sai->pll8k_clk);
  55 +               if (!clk_is_match(pll, npll)) {
  56 +                       if (sai->mclk_streams == 0) {
  57 +                               ret = clk_set_parent(p, npll);
  58 +                               if (ret < 0)
  59 +                                       dev_warn(dai->dev,
  60 +                                               "failed to set parent %s: %d\n",
  61 +                                               __clk_get_name(npll), ret);
  62 +                       } else {
  63 +                               dev_err(dai->dev,
  64 +                                       "PLL %s is in use by a running stream.\n",
  65 +                                       __clk_get_name(pll));
  66 +                               return -EINVAL;
  67 +                       }
  68 +               }
  69 +       }
  70 +
  71 +       ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
  72 +       if (ret < 0)
  73 +               dev_err(dai->dev, "failed to set clock rate (%u): %d\n",
  74 +                               freq, ret);
  75 +       return ret;
  76 +}
  77 +
  78  static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  79  {
  80         struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
  81 @@ -262,12 +307,9 @@ static int fsl_sai_set_dai_sysclk(struct
  82                         return -EINVAL;
  83                 }
  84
  85 -               ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
  86 -               if (ret < 0) {
  87 -                       dev_err(cpu_dai->dev, "failed to set clock rate (%u): %d\n",
  88 -                                       freq, ret);
  89 +               ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
  90 +               if (ret < 0)
  91                         return ret;
  92 -               }
  93         }
  94
  95         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
  96 @@ -1288,6 +1330,14 @@ static int fsl_sai_probe(struct platform
  97                 }
  98         }
  99
 100 +       sai->pll8k_clk = devm_clk_get(&pdev->dev, "pll8k");
 101 +       if (IS_ERR(sai->pll8k_clk))
 102 +               sai->pll8k_clk = NULL;
 103 +
 104 +       sai->pll11k_clk = devm_clk_get(&pdev->dev, "pll11k");
 105 +       if (IS_ERR(sai->pll11k_clk))
 106 +               sai->pll11k_clk = NULL;
 107 +
 108         if (of_find_property(np, "fsl,sai-multi-lane", NULL))
 109                 sai->is_multi_lane = true;
 110
 111 --- a/sound/soc/fsl/fsl_sai.h
 112 +++ b/sound/soc/fsl/fsl_sai.h
 113 @@ -239,6 +239,8 @@ struct fsl_sai {
 114         struct regmap *regmap;
 115         struct clk *bus_clk;
 116         struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
 117 +       struct clk *pll8k_clk;
 118 +       struct clk *pll11k_clk;
 119
 120         bool slave_mode[2];
 121         bool is_lsb_first;