git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 53c3bd0d5a873c23841bb95e7b95c1c3630c50bd Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Thu, 12 Jul 2018 13:03:13 +0300
   4 Subject: [PATCH] at803x: Address packet drops at low traffic rate due to
   5  SmartEEE feature
   6
   7 * According to the AR8035 datasheet, smartEEE mode (active by default)
   8   makes the PHY enters sleep after a configurable idle time. It does
   9   this autonomously, without LPI (Low Power Idle) signals coming from MAC.
  10 * Tested with ping (default of 1 second interval) over back-to-back
  11   RGMII between 2 boards having AR8035 at both ends:
  12     - Without patch:
  13   225 packets transmitted, 145 received, 35% packet loss, time 229334ms
  14     - With patch:
  15   144 packets transmitted, 144 received, 0% packet loss, time 146378ms
  16
  17 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  18 ---
  19  drivers/net/phy/Kconfig  | 10 ++++++++++
  20  drivers/net/phy/at803x.c | 22 ++++++++++++++++++++++
  21  2 files changed, 32 insertions(+)
  22
  23 --- a/drivers/net/phy/Kconfig
  24 +++ b/drivers/net/phy/Kconfig
  25 @@ -371,6 +371,16 @@ config AT803X_PHY
  26         ---help---
  27           Currently supports the AT8030 and AT8035 model
  28
  29 +config AT803X_PHY_SMART_EEE
  30 +       depends on AT803X_PHY
  31 +       default n
  32 +       tristate "SmartEEE feature for AT803X PHYs"
  33 +       ---help---
  34 +         Enables the Atheros SmartEEE feature (not IEEE 802.3az). When 2 PHYs
  35 +         which support this feature are connected back-to-back, they may
  36 +         negotiate a low-power sleep mode autonomously, without the Ethernet
  37 +         controller's knowledge.  May cause packet loss.
  38 +
  39  config BCM63XX_PHY
  40         tristate "Broadcom 63xx SOCs internal PHY"
  41         depends on BCM63XX || COMPILE_TEST
  42 --- a/drivers/net/phy/at803x.c
  43 +++ b/drivers/net/phy/at803x.c
  44 @@ -63,6 +63,8 @@
  45  #define AT803X_DEBUG_REG_5                     0x05
  46  #define AT803X_DEBUG_TX_CLK_DLY_EN             BIT(8)
  47
  48 +#define AT803X_LPI_EN                          BIT(8)
  49 +
  50  #define ATH8030_PHY_ID 0x004dd076
  51  #define ATH8031_PHY_ID 0x004dd074
  52  #define ATH8032_PHY_ID 0x004dd023
  53 @@ -257,6 +259,19 @@ static int at803x_probe(struct phy_devic
  54         return 0;
  55  }
  56
  57 +static void at803x_enable_smart_eee(struct phy_device *phydev, int on)
  58 +{
  59 +       int value;
  60 +
  61 +       /* 5.1.11 Smart_eee control3 */
  62 +       value = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x805D);
  63 +       if (on)
  64 +               value |= AT803X_LPI_EN;
  65 +       else
  66 +               value &= ~AT803X_LPI_EN;
  67 +       phy_write_mmd(phydev, MDIO_MMD_PCS, 0x805D, value);
  68 +}
  69 +
  70  static int at803x_config_init(struct phy_device *phydev)
  71  {
  72         int ret;
  73 @@ -282,6 +297,13 @@ static int at803x_config_init(struct phy
  74                         return ret;
  75         }
  76
  77 +
  78 +#ifdef CONFIG_AT803X_PHY_SMART_EEE
  79 +       at803x_enable_smart_eee(phydev, 1);
  80 +#else
  81 +       at803x_enable_smart_eee(phydev, 0);
  82 +#endif
  83 +
  84         /* The RX and TX delay default is:
  85          *   after HW reset: RX delay enabled and TX delay disabled
  86          *   after SW reset: RX delay enabled, while TX delay retains the