36ac748af0914f1d49b307a7c91e579d8eb241c9
[openwrt/staging/aparcar.git] /
1 From 6e238362b9793bf334c9bed2291b571cbbc75b0b Mon Sep 17 00:00:00 2001
2 From: Florian Fainelli <f.fainelli@gmail.com>
3 Date: Wed, 27 Oct 2021 12:37:29 -0700
4 Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
5
6 The I2C interrupt controller line is off by 32 because the datasheet
7 describes interrupt inputs into the GIC which are for Shared Peripheral
8 Interrupts and are starting at offset 32. The ARM GIC binding expects
9 the SPI interrupts to be numbered from 0 relative to the SPI base.
10
11 Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
13 Tested-by: Christian Lamparter <chunkeey@gmail.com>
14 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
15 ---
16 arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
17 1 file changed, 1 insertion(+), 1 deletion(-)
18
19 --- a/arch/arm/boot/dts/bcm5301x.dtsi
20 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
21 @@ -408,7 +408,7 @@
22 i2c0: i2c@18009000 {
23 compatible = "brcm,iproc-i2c";
24 reg = <0x18009000 0x50>;
25 - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
26 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 clock-frequency = <100000>;