git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 6c753f83ffc3fede13582f667a15e7f6e97f972c Mon Sep 17 00:00:00 2001
   2 From: Robin Gong <yibin.gong@nxp.com>
   3 Date: Tue, 4 Jul 2017 16:04:36 +0800
   4 Subject: [PATCH] MLK-15330-3 dma: fsl-edma-v3: add dual fifo support
   5
   6 There is Audio dual fifo cause that fill fifo one by one and
   7 loop back after every minor loop:
   8   -- fill the first 32bit width fifo
   9   -- fill the next 32bit width fifo
  10   -- +MLOFF signed offset after the above two FIFOs filled
  11   -- loop back to the first step to handle the next minor loop.
  12
  13 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  14 (cherry picked from commit 5aa5e9663bb3a834444b75ea086bef8c37ecb636)
  15 ---
  16  .../devicetree/bindings/dma/fsl-edma-v3.txt        |  2 ++
  17  drivers/dma/fsl-edma-v3.c                          | 29 ++++++++++++++++++++--
  18  2 files changed, 29 insertions(+), 2 deletions(-)
  19
  20 --- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  21 +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
  22 @@ -22,6 +22,8 @@ Required properties:
  23                 0: transmit, 1: receive.
  24         BIT(1): local or remote access:
  25                 0: local, 1: remote.
  26 +       BIT(2): dualfifo case or not(only in Audio cyclic now):
  27 +               0: not dual fifo case, 1: dualfifo case.
  28         See the SoC's reference manual for all the supported request sources.
  29  - dma-channels : Number of channels supported by the controller
  30
  31 --- a/drivers/dma/fsl-edma-v3.c
  32 +++ b/drivers/dma/fsl-edma-v3.c
  33 @@ -78,6 +78,9 @@
  34
  35  #define EDMA_TCD_SOFF_SOFF(x)          (x)
  36  #define EDMA_TCD_NBYTES_NBYTES(x)      (x)
  37 +#define EDMA_TCD_NBYTES_MLOFF(x)       (x << 10)
  38 +#define EDMA_TCD_NBYTES_DMLOE          (1 << 30)
  39 +#define EDMA_TCD_NBYTES_SMLOE          (1 << 31)
  40  #define EDMA_TCD_SLAST_SLAST(x)                (x)
  41  #define EDMA_TCD_DADDR_DADDR(x)                (x)
  42  #define EDMA_TCD_CITER_CITER(x)                ((x) & 0x7FFF)
  43 @@ -102,6 +105,7 @@
  44
  45  #define ARGS_RX                                BIT(0)
  46  #define ARGS_REMOTE                    BIT(1)
  47 +#define ARGS_DFIFO                     BIT(2)
  48
  49  struct fsl_edma3_hw_tcd {
  50         __le32  saddr;
  51 @@ -143,6 +147,7 @@ struct fsl_edma3_chan {
  52         int                             priority;
  53         int                             is_rxchan;
  54         int                             is_remote;
  55 +       int                             is_dfifo;
  56         struct dma_pool                 *tcd_pool;
  57         u32                             chn_real_count;
  58         char                            txirq_name[32];
  59 @@ -454,6 +459,19 @@ void fsl_edma3_fill_tcd(struct fsl_edma3
  60
  61         tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff));
  62
  63 +       if (fsl_chan->is_dfifo) {
  64 +               /* set mloff as -8 */
  65 +               nbytes |= EDMA_TCD_NBYTES_MLOFF(-8);
  66 +               /* enable DMLOE/SMLOE */
  67 +               if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
  68 +                       nbytes |= EDMA_TCD_NBYTES_DMLOE;
  69 +                       nbytes &= ~EDMA_TCD_NBYTES_SMLOE;
  70 +               } else {
  71 +                       nbytes |= EDMA_TCD_NBYTES_SMLOE;
  72 +                       nbytes &= ~EDMA_TCD_NBYTES_DMLOE;
  73 +               }
  74 +       }
  75 +
  76         tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes));
  77         tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast));
  78
  79 @@ -540,11 +558,17 @@ static struct dma_async_tx_descriptor *f
  80                         src_addr = dma_buf_next;
  81                         dst_addr = fsl_chan->fsc.dev_addr;
  82                         soff = fsl_chan->fsc.addr_width;
  83 -                       doff = 0;
  84 +                       if (fsl_chan->is_dfifo)
  85 +                               doff = 4;
  86 +                       else
  87 +                               doff = 0;
  88                 } else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) {
  89                         src_addr = fsl_chan->fsc.dev_addr;
  90                         dst_addr = dma_buf_next;
  91 -                       soff = 0;
  92 +                       if (fsl_chan->is_dfifo)
  93 +                               soff = 4;
  94 +                       else
  95 +                               soff = 0;
  96                         doff = fsl_chan->fsc.addr_width;
  97                 } else {
  98                         /* DMA_DEV_TO_DEV */
  99 @@ -715,6 +739,7 @@ static struct dma_chan *fsl_edma3_xlate(
 100                         fsl_chan->priority = dma_spec->args[1];
 101                         fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
 102                         fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
 103 +                       fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO;
 104                         mutex_unlock(&fsl_edma3->fsl_edma3_mutex);
 105                         return chan;
 106                 }