git.openwrt.org Git - openwrt/staging/jogo.git/blob

   1 From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Thu, 12 Nov 2020 16:08:32 +0100
   4 Subject: [PATCH] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early
   5  DTS files
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 They don't descibe hardware fully yet but it's enough to boot a system.
  11
  12 Some missing blocks:
  13 1. PMC (Power Management Controller?)
  14 2. Ethernet
  15 3. Crypto
  16 4. Thermal
  17
  18 Asus DTS is missing defining full NAND partitions layout and buttons.
  19
  20 Further changes will fill those gaps as soon as required bindings will
  21 be found / tested / added.
  22
  23 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  24 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  25 ---
  26  arch/arm64/boot/dts/broadcom/Makefile         |   1 +
  27  arch/arm64/boot/dts/broadcom/bcm4908/Makefile |   2 +
  28  .../bcm4908/bcm4908-asus-gt-ac5300.dts        |  66 +++++++
  29  .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 187 ++++++++++++++++++
  30  4 files changed, 256 insertions(+)
  31  create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile
  32  create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
  33  create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
  34
  35 --- a/arch/arm64/boot/dts/broadcom/Makefile
  36 +++ b/arch/arm64/boot/dts/broadcom/Makefile
  37 @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rp
  38                               bcm2837-rpi-3-b-plus.dtb \
  39                               bcm2837-rpi-cm3-io3.dtb
  40
  41 +subdir-y       += bcm4908
  42  subdir-y       += northstar2
  43  subdir-y       += stingray
  44 --- /dev/null
  45 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
  46 @@ -0,0 +1,2 @@
  47 +# SPDX-License-Identifier: GPL-2.0
  48 +dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
  49 --- /dev/null
  50 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
  51 @@ -0,0 +1,66 @@
  52 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  53 +
  54 +#include <dt-bindings/gpio/gpio.h>
  55 +#include <dt-bindings/input/input.h>
  56 +
  57 +#include "bcm4908.dtsi"
  58 +
  59 +/ {
  60 +       compatible = "asus,gt-ac5300", "brcm,bcm4908";
  61 +       model = "Asus GT-AC5300";
  62 +
  63 +       memory@0 {
  64 +               device_type = "memory";
  65 +               reg = <0x00 0x00 0x00 0x40000000>;
  66 +       };
  67 +
  68 +       gpio-keys-polled {
  69 +               compatible = "gpio-keys-polled";
  70 +               poll-interval = <100>;
  71 +
  72 +               wifi {
  73 +                       label = "WiFi";
  74 +                       linux,code = <KEY_RFKILL>;
  75 +                       gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
  76 +               };
  77 +
  78 +               wps {
  79 +                       label = "WPS";
  80 +                       linux,code = <KEY_WPS_BUTTON>;
  81 +                       gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
  82 +               };
  83 +
  84 +               restart {
  85 +                       label = "Reset";
  86 +                       linux,code = <KEY_RESTART>;
  87 +                       gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
  88 +               };
  89 +
  90 +               brightness {
  91 +                       label = "LEDs";
  92 +                       linux,code = <KEY_BRIGHTNESS_ZERO>;
  93 +                       gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
  94 +               };
  95 +       };
  96 +};
  97 +
  98 +&nandcs {
  99 +       nand-ecc-strength = <4>;
 100 +       nand-ecc-step-size = <512>;
 101 +       nand-on-flash-bbt;
 102 +       brcm,nand-has-wp;
 103 +
 104 +       #address-cells = <1>;
 105 +       #size-cells = <0>;
 106 +
 107 +       partitions {
 108 +               compatible = "fixed-partitions";
 109 +               #address-cells = <1>;
 110 +               #size-cells = <1>;
 111 +
 112 +               partition@0 {
 113 +                       label = "cferom";
 114 +                       reg = <0x0 0x100000>;
 115 +               };
 116 +       };
 117 +};
 118 --- /dev/null
 119 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
 120 @@ -0,0 +1,187 @@
 121 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 122 +
 123 +#include <dt-bindings/interrupt-controller/irq.h>
 124 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 125 +
 126 +/dts-v1/;
 127 +
 128 +/ {
 129 +       interrupt-parent = <&gic>;
 130 +
 131 +       #address-cells = <2>;
 132 +       #size-cells = <2>;
 133 +
 134 +       aliases {
 135 +               serial0 = &uart0;
 136 +       };
 137 +
 138 +       chosen {
 139 +               stdout-path = "serial0:115200n8";
 140 +       };
 141 +
 142 +       cpus {
 143 +               #address-cells = <1>;
 144 +               #size-cells = <0>;
 145 +
 146 +               cpu0: cpu@0 {
 147 +                       device_type = "cpu";
 148 +                       compatible = "brcm,brahma-b53";
 149 +                       reg = <0x0>;
 150 +                       next-level-cache = <&l2>;
 151 +               };
 152 +
 153 +               cpu1: cpu@1 {
 154 +                       device_type = "cpu";
 155 +                       compatible = "brcm,brahma-b53";
 156 +                       reg = <0x1>;
 157 +                       enable-method = "spin-table";
 158 +                       cpu-release-addr = <0x0 0xfff8>;
 159 +                       next-level-cache = <&l2>;
 160 +               };
 161 +
 162 +               cpu2: cpu@2 {
 163 +                       device_type = "cpu";
 164 +                       compatible = "brcm,brahma-b53";
 165 +                       reg = <0x2>;
 166 +                       enable-method = "spin-table";
 167 +                       cpu-release-addr = <0x0 0xfff8>;
 168 +                       next-level-cache = <&l2>;
 169 +               };
 170 +
 171 +               cpu3: cpu@3 {
 172 +                       device_type = "cpu";
 173 +                       compatible = "brcm,brahma-b53";
 174 +                       reg = <0x3>;
 175 +                       enable-method = "spin-table";
 176 +                       cpu-release-addr = <0x0 0xfff8>;
 177 +                       next-level-cache = <&l2>;
 178 +               };
 179 +
 180 +               l2: l2-cache0 {
 181 +                       compatible = "cache";
 182 +               };
 183 +       };
 184 +
 185 +       axi@81000000 {
 186 +               compatible = "simple-bus";
 187 +               #address-cells = <1>;
 188 +               #size-cells = <1>;
 189 +               ranges = <0x00 0x00 0x81000000 0x4000>;
 190 +
 191 +               gic: interrupt-controller@1000 {
 192 +                       compatible = "arm,gic-400";
 193 +                       #interrupt-cells = <3>;
 194 +                       #address-cells = <0>;
 195 +                       interrupt-controller;
 196 +                       reg = <0x1000 0x1000>,
 197 +                             <0x2000 0x2000>;
 198 +               };
 199 +       };
 200 +
 201 +       timer {
 202 +               compatible = "arm,armv8-timer";
 203 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 204 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 205 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 206 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 207 +       };
 208 +
 209 +       pmu {
 210 +               compatible = "arm,cortex-a53-pmu";
 211 +               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 212 +                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 213 +                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 214 +                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 215 +               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 216 +       };
 217 +
 218 +       clocks {
 219 +               periph_clk: periph_clk {
 220 +                       compatible = "fixed-clock";
 221 +                       #clock-cells = <0>;
 222 +                       clock-frequency = <50000000>;
 223 +                       clock-output-names = "periph";
 224 +               };
 225 +       };
 226 +
 227 +       soc {
 228 +               compatible = "simple-bus";
 229 +               #address-cells = <1>;
 230 +               #size-cells = <1>;
 231 +               ranges = <0x00 0x00 0x80000000 0x10000>;
 232 +
 233 +               usb@c300 {
 234 +                       compatible = "generic-ehci";
 235 +                       reg = <0xc300 0x100>;
 236 +                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 237 +                       status = "disabled";
 238 +               };
 239 +
 240 +               usb@c400 {
 241 +                       compatible = "generic-ohci";
 242 +                       reg = <0xc400 0x100>;
 243 +                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 244 +                       status = "disabled";
 245 +               };
 246 +
 247 +               usb@d000 {
 248 +                       compatible = "generic-xhci";
 249 +                       reg = <0xd000 0x8c8>;
 250 +                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 251 +                       status = "disabled";
 252 +               };
 253 +       };
 254 +
 255 +       bus@ff800000 {
 256 +               compatible = "simple-bus";
 257 +               #address-cells = <1>;
 258 +               #size-cells = <1>;
 259 +               ranges = <0x00 0x00 0xff800000 0x3000>;
 260 +
 261 +               timer: timer@400 {
 262 +                       compatible = "brcm,bcm6328-timer", "syscon";
 263 +                       reg = <0x400 0x3c>;
 264 +               };
 265 +
 266 +               gpio0: gpio-controller@500 {
 267 +                       compatible = "brcm,bcm6345-gpio";
 268 +                       reg-names = "dirout", "dat";
 269 +                       reg = <0x500 0x28>, <0x528 0x28>;
 270 +
 271 +                       #gpio-cells = <2>;
 272 +                       gpio-controller;
 273 +               };
 274 +
 275 +               uart0: serial@640 {
 276 +                       compatible = "brcm,bcm6345-uart";
 277 +                       reg = <0x640 0x18>;
 278 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 279 +                       clocks = <&periph_clk>;
 280 +                       clock-names = "periph";
 281 +                       status = "okay";
 282 +               };
 283 +
 284 +               nand@1800 {
 285 +                       #address-cells = <1>;
 286 +                       #size-cells = <0>;
 287 +                       compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
 288 +                       reg = <0x1800 0x600>, <0x2000 0x10>;
 289 +                       reg-names = "nand", "nand-int-base";
 290 +                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 291 +                       interrupt-names = "nand";
 292 +                       status = "okay";
 293 +
 294 +                       nandcs: nandcs@0 {
 295 +                               compatible = "brcm,nandcs";
 296 +                               reg = <0>;
 297 +                       };
 298 +               };
 299 +
 300 +               reboot {
 301 +                       compatible = "syscon-reboot";
 302 +                       regmap = <&timer>;
 303 +                       offset = <0x34>;
 304 +                       mask = <1>;
 305 +               };
 306 +       };
 307 +};