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1 From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
3 Date: Thu, 23 Sep 2021 19:20:13 +0200
4 Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel
5 implementation
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Remove old RPC implementation and add a new native kernel implementation.
11
12 The old implementation uses ARM SMC API to issue RPC calls to ARM Trusted
13 Firmware which provides real implementation of PHY configuration.
14
15 But older versions of ARM Trusted Firmware do not provide this PHY
16 configuration functionality, simply returning: operation not supported; or
17 worse, some versions provide the configuration functionality incorrectly.
18
19 For example the firmware shipped in ESPRESSObin board has this older
20 version of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe
21 functionality do not work with newer versions of Linux kernel.
22
23 Due to the above reasons, the following commits were introduced into Linux,
24 to workaround these issues by ignoring -EOPNOTSUPP error code from
25 phy-mvebu-a3700-comphy driver function phy_power_on():
26
27 commit 45aefe3d2251 ("ata: ahci: mvebu: Make SATA PHY optional for Armada
28 3720")
29 commit 3241929b67d2 ("usb: host: xhci: mvebu: make USB 3.0 PHY optional for
30 Armada 3720")
31 commit b0c6ae0f8948 ("PCI: aardvark: Fix initialization with old Marvell's
32 Arm Trusted Firmware")
33
34 Replace this RPC implementation with proper native kernel implementation,
35 which is independent on the firmware. Never return -EOPNOTSUPP for proper
36 arguments.
37
38 This should solve multiple issues with real-world boards, where it is not
39 possible or really inconvenient to change the firmware. Let's eliminate
40 these issues.
41
42 This implementation is ported directly from Armada 3720 comphy driver found
43 in newest version of ARM Trusted Firmware source code, but with various
44 fixes of register names, some added comments, some refactoring due to the
45 original code not conforming to kernel standards. Also PCIe mode poweroff
46 support was added here, and PHY reset support. These changes are also going
47 to be sent to ARM Trusted Firmware.
48
49 Signed-off-by: Pali Rohár <pali@kernel.org>
50 Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
51 [ Pali did the porting from ATF.
52 I (Marek) then fixed some register names, some various other things,
53 added some comments and refactored the code to kernel standards. Also
54 fixed PHY poweroff and added PHY reset. ]
55 Signed-off-by: Marek Behún <kabel@kernel.org>
56 ---
57 drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--
58 1 file changed, 1234 insertions(+), 117 deletions(-)
59
60 diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
61 index dbb2d4308851..cbda47c33b98 100644
62 --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
63 +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
64 @@ -5,12 +5,16 @@
65 * Authors:
66 * Evan Wang <xswang@marvell.com>
67 * Miquèl Raynal <miquel.raynal@bootlin.com>
68 + * Pali Rohár <pali@kernel.org>
69 + * Marek Behún <kabel@kernel.org>
70 *
71 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
72 - * SMC call initial support done by Grzegorz Jaszczyk.
73 + * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org>
74 + * and Marek Behún <kabel@kernel.org>.
75 */
76
77 -#include <linux/arm-smccc.h>
78 +#include <linux/bitfield.h>
79 +#include <linux/clk.h>
80 #include <linux/io.h>
81 #include <linux/iopoll.h>
82 #include <linux/mfd/syscon.h>
83 @@ -18,103 +22,1147 @@
84 #include <linux/phy.h>
85 #include <linux/phy/phy.h>
86 #include <linux/platform_device.h>
87 +#include <linux/spinlock.h>
88
89 -#define MVEBU_A3700_COMPHY_LANES 3
90 -
91 -/* COMPHY Fast SMC function identifiers */
92 -#define COMPHY_SIP_POWER_ON 0x82000001
93 -#define COMPHY_SIP_POWER_OFF 0x82000002
94 -#define COMPHY_SIP_PLL_LOCK 0x82000003
95 -
96 -#define COMPHY_FW_MODE_SATA 0x1
97 -#define COMPHY_FW_MODE_SGMII 0x2
98 -#define COMPHY_FW_MODE_2500BASEX 0x3
99 -#define COMPHY_FW_MODE_USB3H 0x4
100 -#define COMPHY_FW_MODE_USB3D 0x5
101 -#define COMPHY_FW_MODE_PCIE 0x6
102 -#define COMPHY_FW_MODE_USB3 0xa
103 -
104 -#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
105 -#define COMPHY_FW_SPEED_2_5G 1
106 -#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
107 -#define COMPHY_FW_SPEED_5G 3
108 -#define COMPHY_FW_SPEED_MAX 0x3F
109 -
110 -#define COMPHY_FW_MODE(mode) ((mode) << 12)
111 -#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
112 - ((idx) << 8) | \
113 - ((speed) << 2))
114 -#define COMPHY_FW_PCIE(mode, speed, width) (COMPHY_FW_NET(mode, 0, speed) | \
115 - ((width) << 18))
116 +#define PLL_SET_DELAY_US 600
117 +#define COMPHY_PLL_SLEEP 1000
118 +#define COMPHY_PLL_TIMEOUT 150000
119 +
120 +/* Comphy lane2 indirect access register offset */
121 +#define COMPHY_LANE2_INDIR_ADDR 0x0
122 +#define COMPHY_LANE2_INDIR_DATA 0x4
123 +
124 +/* SATA and USB3 PHY offset compared to SATA PHY */
125 +#define COMPHY_LANE2_REGS_BASE 0x200
126 +
127 +/*
128 + * When accessing common PHY lane registers directly, we need to shift by 1,
129 + * since the registers are 16-bit.
130 + */
131 +#define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
132 +
133 +/* COMPHY registers */
134 +#define COMPHY_POWER_PLL_CTRL 0x01
135 +#define PU_IVREF_BIT BIT(15)
136 +#define PU_PLL_BIT BIT(14)
137 +#define PU_RX_BIT BIT(13)
138 +#define PU_TX_BIT BIT(12)
139 +#define PU_TX_INTP_BIT BIT(11)
140 +#define PU_DFE_BIT BIT(10)
141 +#define RESET_DTL_RX_BIT BIT(9)
142 +#define PLL_LOCK_BIT BIT(8)
143 +#define REF_FREF_SEL_MASK GENMASK(4, 0)
144 +#define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
145 +#define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
146 +#define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
147 +#define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
148 +#define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
149 +#define COMPHY_MODE_MASK GENMASK(7, 5)
150 +#define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0)
151 +#define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3)
152 +#define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4)
153 +#define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5)
154 +
155 +#define COMPHY_KVCO_CAL_CTRL 0x02
156 +#define USE_MAX_PLL_RATE_BIT BIT(12)
157 +#define SPEED_PLL_MASK GENMASK(7, 2)
158 +#define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10)
159 +
160 +#define COMPHY_DIG_LOOPBACK_EN 0x23
161 +#define SEL_DATA_WIDTH_MASK GENMASK(11, 10)
162 +#define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)
163 +#define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)
164 +#define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)
165 +#define PLL_READY_TX_BIT BIT(4)
166 +
167 +#define COMPHY_SYNC_PATTERN 0x24
168 +#define TXD_INVERT_BIT BIT(10)
169 +#define RXD_INVERT_BIT BIT(11)
170 +
171 +#define COMPHY_SYNC_MASK_GEN 0x25
172 +#define PHY_GEN_MAX_MASK GENMASK(11, 10)
173 +#define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1)
174 +
175 +#define COMPHY_ISOLATION_CTRL 0x26
176 +#define PHY_ISOLATE_MODE BIT(15)
177 +
178 +#define COMPHY_GEN2_SET2 0x3e
179 +#define GS2_TX_SSC_AMP_MASK GENMASK(15, 9)
180 +#define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)
181 +#define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7)
182 +#define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
183 + 0x0)
184 +#define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
185 + 0x1)
186 +#define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
187 + 0x2)
188 +#define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
189 + 0x3)
190 +#define GS2_RSVD_6_0_MASK GENMASK(6, 0)
191 +
192 +#define COMPHY_GEN3_SET2 0x3f
193 +
194 +#define COMPHY_IDLE_SYNC_EN 0x48
195 +#define IDLE_SYNC_EN BIT(12)
196 +
197 +#define COMPHY_MISC_CTRL0 0x4F
198 +#define CLK100M_125M_EN BIT(4)
199 +#define TXDCLK_2X_SEL BIT(6)
200 +#define CLK500M_EN BIT(7)
201 +#define PHY_REF_CLK_SEL BIT(10)
202 +
203 +#define COMPHY_SFT_RESET 0x52
204 +#define SFT_RST BIT(9)
205 +#define SFT_RST_NO_REG BIT(10)
206 +
207 +#define COMPHY_MISC_CTRL1 0x73
208 +#define SEL_BITS_PCIE_FORCE BIT(15)
209 +
210 +#define COMPHY_GEN2_SET3 0x112
211 +#define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0)
212 +#define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)
213 +
214 +/* PIPE registers */
215 +#define COMPHY_PIPE_LANE_CFG0 0x180
216 +#define PRD_TXDEEMPH0_MASK BIT(0)
217 +#define PRD_TXMARGIN_MASK GENMASK(3, 1)
218 +#define PRD_TXSWING_MASK BIT(4)
219 +#define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5)
220 +
221 +#define COMPHY_PIPE_LANE_CFG1 0x181
222 +#define PRD_TXDEEMPH1_MASK BIT(15)
223 +#define USE_MAX_PLL_RATE_EN BIT(9)
224 +#define TX_DET_RX_MODE BIT(6)
225 +#define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
226 +#define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
227 +#define TX_ELEC_IDLE_MODE_EN BIT(0)
228 +
229 +#define COMPHY_PIPE_LANE_STAT1 0x183
230 +#define TXDCLK_PCLK_EN BIT(0)
231 +
232 +#define COMPHY_PIPE_LANE_CFG4 0x188
233 +#define SPREAD_SPECTRUM_CLK_EN BIT(7)
234 +
235 +#define COMPHY_PIPE_RST_CLK_CTRL 0x1C1
236 +#define PIPE_SOFT_RESET BIT(0)
237 +#define PIPE_REG_RESET BIT(1)
238 +#define MODE_CORE_CLK_FREQ_SEL BIT(9)
239 +#define MODE_PIPE_WIDTH_32 BIT(3)
240 +#define MODE_REFDIV_MASK GENMASK(5, 4)
241 +#define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2)
242 +
243 +#define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2
244 +#define MODE_MARGIN_OVERRIDE BIT(2)
245 +
246 +#define COMPHY_PIPE_CLK_SRC_LO 0x1C3
247 +#define MODE_CLK_SRC BIT(0)
248 +#define BUNDLE_PERIOD_SEL BIT(1)
249 +#define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
250 +#define BUNDLE_SAMPLE_CTRL BIT(4)
251 +#define PLL_READY_DLY_MASK GENMASK(7, 5)
252 +#define CFG_SEL_20B BIT(15)
253 +
254 +#define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0
255 +#define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)
256 +#define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8)
257 +#define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)
258 +#define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0)
259 +#define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)
260 +#define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)
261 +
262 +/*
263 + * This register is not from PHY lane register space. It only exists in the
264 + * indirect register space, before the actual PHY lane 2 registers. So the
265 + * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE.
266 + * It is used only for SATA PHY initialization.
267 + */
268 +#define COMPHY_RESERVED_REG 0x0E
269 +#define PHYCTRL_FRM_PIN_BIT BIT(13)
270 +
271 +/* South Bridge PHY Configuration Registers */
272 +#define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
273 +
274 +/*
275 + * lane0: USB3/GbE1 PHY Configuration 1
276 + * lane1: PCIe/GbE0 PHY Configuration 1
277 + * (used only by SGMII code)
278 + */
279 +#define COMPHY_PHY_CFG1 0x0
280 +#define PIN_PU_IVREF_BIT BIT(1)
281 +#define PIN_RESET_CORE_BIT BIT(11)
282 +#define PIN_RESET_COMPHY_BIT BIT(12)
283 +#define PIN_PU_PLL_BIT BIT(16)
284 +#define PIN_PU_RX_BIT BIT(17)
285 +#define PIN_PU_TX_BIT BIT(18)
286 +#define PIN_TX_IDLE_BIT BIT(19)
287 +#define GEN_RX_SEL_MASK GENMASK(25, 22)
288 +#define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val))
289 +#define GEN_TX_SEL_MASK GENMASK(29, 26)
290 +#define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val))
291 +#define SERDES_SPEED_1_25_G 0x6
292 +#define SERDES_SPEED_3_125_G 0x8
293 +#define PHY_RX_INIT_BIT BIT(30)
294 +
295 +/*
296 + * lane0: USB3/GbE1 PHY Status 1
297 + * lane1: PCIe/GbE0 PHY Status 1
298 + * (used only by SGMII code)
299 + */
300 +#define COMPHY_PHY_STAT1 0x18
301 +#define PHY_RX_INIT_DONE_BIT BIT(0)
302 +#define PHY_PLL_READY_RX_BIT BIT(2)
303 +#define PHY_PLL_READY_TX_BIT BIT(3)
304 +
305 +/* PHY Selector */
306 +#define COMPHY_SELECTOR_PHY_REG 0xFC
307 +/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
308 +#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
309 +/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
310 +#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
311 +/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
312 +#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
313
314 struct mvebu_a3700_comphy_conf {
315 unsigned int lane;
316 enum phy_mode mode;
317 int submode;
318 - u32 fw_mode;
319 };
320
321 -#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw) \
322 +#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \
323 { \
324 .lane = _lane, \
325 .mode = _mode, \
326 .submode = _smode, \
327 - .fw_mode = _fw, \
328 }
329
330 -#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \
331 - MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)
332 +#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \
333 + MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA)
334
335 -#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \
336 - MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)
337 +#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \
338 + MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode)
339
340 static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
341 /* lane 0 */
342 - MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,
343 - COMPHY_FW_MODE_USB3H),
344 - MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,
345 - COMPHY_FW_MODE_SGMII),
346 - MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,
347 - COMPHY_FW_MODE_2500BASEX),
348 + MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS),
349 + MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII),
350 + MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX),
351 + MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX),
352 /* lane 1 */
353 - MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
354 - MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,
355 - COMPHY_FW_MODE_SGMII),
356 - MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,
357 - COMPHY_FW_MODE_2500BASEX),
358 + MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE),
359 + MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII),
360 + MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX),
361 + MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX),
362 /* lane 2 */
363 - MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
364 - MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,
365 - COMPHY_FW_MODE_USB3H),
366 + MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA),
367 + MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS),
368 +};
369 +
370 +struct mvebu_a3700_comphy_priv {
371 + void __iomem *comphy_regs;
372 + void __iomem *lane0_phy_regs; /* USB3 and GbE1 */
373 + void __iomem *lane1_phy_regs; /* PCIe and GbE0 */
374 + void __iomem *lane2_phy_indirect; /* SATA and USB3 */
375 + spinlock_t lock; /* for PHY selector access */
376 + bool xtal_is_40m;
377 };
378
379 struct mvebu_a3700_comphy_lane {
380 + struct mvebu_a3700_comphy_priv *priv;
381 struct device *dev;
382 unsigned int id;
383 enum phy_mode mode;
384 int submode;
385 + bool invert_tx;
386 + bool invert_rx;
387 + bool needs_reset;
388 };
389
390 -static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
391 - unsigned long mode)
392 +struct gbe_phy_init_data_fix {
393 + u16 addr;
394 + u16 value;
395 +};
396 +
397 +/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
398 +static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {
399 + { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 },
400 + { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 },
401 + { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 },
402 + { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC },
403 + { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 },
404 + { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 },
405 + { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },
406 + { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },
407 + { 0x104, 0x0C10 }
408 +};
409 +
410 +/* 40M1G25 mode init data */
411 +static u16 gbe_phy_init[512] = {
412 + /* 0 1 2 3 4 5 6 7 */
413 + /*-----------------------------------------------------------*/
414 + /* 8 9 A B C D E F */
415 + 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
416 + 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
417 + 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
418 + 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
419 + 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
420 + 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
421 + 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
422 + 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
423 + 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
424 + 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
425 + 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
426 + 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
427 + 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
428 + 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
429 + 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
430 + 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
431 + 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
432 + 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
433 + 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
434 + 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
435 + 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
436 + 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
437 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
438 + 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
439 + 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
440 + 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
441 + 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
442 + 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
443 + 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
444 + 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
445 + 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
446 + 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
447 + 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
448 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
449 + 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
450 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
451 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
452 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
453 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
454 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
455 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
456 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
457 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
458 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
459 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
460 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
461 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
462 + 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
463 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
464 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
465 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
466 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
467 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
468 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
469 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
470 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
471 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
472 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
473 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
474 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
475 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
476 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
477 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
478 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
479 +};
480 +
481 +static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)
482 +{
483 + u32 val;
484 +
485 + val = readl(addr);
486 + val = (val & ~mask) | (data & mask);
487 + writel(val, addr);
488 +}
489 +
490 +static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
491 {
492 - struct arm_smccc_res res;
493 - s32 ret;
494 + u16 val;
495
496 - arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
497 - ret = res.a0;
498 + val = readw(addr);
499 + val = (val & ~mask) | (data & mask);
500 + writew(val, addr);
501 +}
502
503 - switch (ret) {
504 - case SMCCC_RET_SUCCESS:
505 - return 0;
506 - case SMCCC_RET_NOT_SUPPORTED:
507 - return -EOPNOTSUPP;
508 +/* Used for accessing lane 2 registers (SATA/USB3 PHY) */
509 +static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv,
510 + u32 offset, u16 data, u16 mask)
511 +{
512 + writel(offset,
513 + priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR);
514 + comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA,
515 + data, mask);
516 +}
517 +
518 +static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,
519 + u16 reg, u16 data, u16 mask)
520 +{
521 + if (lane->id == 2) {
522 + /* lane 2 PHY registers are accessed indirectly */
523 + comphy_set_indirect(lane->priv,
524 + reg + COMPHY_LANE2_REGS_BASE,
525 + data, mask);
526 + } else {
527 + void __iomem *base = lane->id == 1 ?
528 + lane->priv->lane1_phy_regs :
529 + lane->priv->lane0_phy_regs;
530 +
531 + comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg),
532 + data, mask);
533 + }
534 +}
535 +
536 +static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,
537 + u16 reg, u16 bits,
538 + ulong sleep_us, ulong timeout_us)
539 +{
540 + int ret;
541 +
542 + if (lane->id == 2) {
543 + u32 data;
544 +
545 + /* lane 2 PHY registers are accessed indirectly */
546 + writel(reg + COMPHY_LANE2_REGS_BASE,
547 + lane->priv->lane2_phy_indirect +
548 + COMPHY_LANE2_INDIR_ADDR);
549 +
550 + ret = readl_poll_timeout(lane->priv->lane2_phy_indirect +
551 + COMPHY_LANE2_INDIR_DATA,
552 + data, (data & bits) == bits,
553 + sleep_us, timeout_us);
554 + } else {
555 + void __iomem *base = lane->id == 1 ?
556 + lane->priv->lane1_phy_regs :
557 + lane->priv->lane0_phy_regs;
558 + u16 data;
559 +
560 + ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg),
561 + data, (data & bits) == bits,
562 + sleep_us, timeout_us);
563 + }
564 +
565 + return ret;
566 +}
567 +
568 +static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,
569 + u8 reg, u32 data, u32 mask)
570 +{
571 + comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),
572 + data, mask);
573 +}
574 +
575 +static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,
576 + u8 reg, u32 bits,
577 + ulong sleep_us, ulong timeout_us)
578 +{
579 + u32 data;
580 +
581 + return readl_poll_timeout(lane->priv->comphy_regs +
582 + COMPHY_PHY_REG(lane->id, reg),
583 + data, (data & bits) == bits,
584 + sleep_us, timeout_us);
585 +}
586 +
587 +/* PHY selector configures with corresponding modes */
588 +static int
589 +mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)
590 +{
591 + u32 old, new, clr = 0, set = 0;
592 + unsigned long flags;
593 +
594 + switch (lane->mode) {
595 + case PHY_MODE_SATA:
596 + /* SATA must be in Lane2 */
597 + if (lane->id == 2)
598 + clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
599 + else
600 + goto error;
601 + break;
602 +
603 + case PHY_MODE_ETHERNET:
604 + if (lane->id == 0)
605 + clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
606 + else if (lane->id == 1)
607 + clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
608 + else
609 + goto error;
610 + break;
611 +
612 + case PHY_MODE_USB_HOST_SS:
613 + if (lane->id == 2)
614 + set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
615 + else if (lane->id == 0)
616 + set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
617 + else
618 + goto error;
619 + break;
620 +
621 + case PHY_MODE_PCIE:
622 + /* PCIE must be in Lane1 */
623 + if (lane->id == 1)
624 + set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
625 + else
626 + goto error;
627 + break;
628 +
629 + default:
630 + goto error;
631 + }
632 +
633 + spin_lock_irqsave(&lane->priv->lock, flags);
634 +
635 + old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
636 + new = (old & ~clr) | set;
637 + writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
638 +
639 + spin_unlock_irqrestore(&lane->priv->lock, flags);
640 +
641 + dev_dbg(lane->dev,
642 + "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n",
643 + lane->id, lane->mode, old, new);
644 +
645 + return 0;
646 +error:
647 + dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id,
648 + lane->mode);
649 + return -EINVAL;
650 +}
651 +
652 +static int
653 +mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)
654 +{
655 + u32 mask, data, ref_clk;
656 + int ret;
657 +
658 + /* Configure phy selector for SATA */
659 + ret = mvebu_a3700_comphy_set_phy_selector(lane);
660 + if (ret)
661 + return ret;
662 +
663 + /* Clear phy isolation mode to make it work in normal mode */
664 + comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
665 + 0x0, PHY_ISOLATE_MODE);
666 +
667 + /* 0. Check the Polarity invert bits */
668 + data = 0x0;
669 + if (lane->invert_tx)
670 + data |= TXD_INVERT_BIT;
671 + if (lane->invert_rx)
672 + data |= RXD_INVERT_BIT;
673 + mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
674 + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
675 +
676 + /* 1. Select 40-bit data width */
677 + comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
678 + DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK);
679 +
680 + /* 2. Select reference clock(25M) and PHY mode (SATA) */
681 + if (lane->priv->xtal_is_40m)
682 + ref_clk = REF_FREF_SEL_SERDES_40MHZ;
683 + else
684 + ref_clk = REF_FREF_SEL_SERDES_25MHZ;
685 +
686 + data = ref_clk | COMPHY_MODE_SATA;
687 + mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK;
688 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
689 +
690 + /* 3. Use maximum PLL rate (no power save) */
691 + comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
692 + USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT);
693 +
694 + /* 4. Reset reserved bit */
695 + comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,
696 + 0x0, PHYCTRL_FRM_PIN_BIT);
697 +
698 + /* 5. Set vendor-specific configuration (It is done in sata driver) */
699 + /* XXX: in U-Boot below sequence was executed in this place, in Linux
700 + * not. Now it is done only in U-Boot before this comphy
701 + * initialization - tests shows that it works ok, but in case of any
702 + * future problem it is left for reference.
703 + * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);
704 + * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));
705 + */
706 +
707 + /* Wait for > 55 us to allow PLL be enabled */
708 + udelay(PLL_SET_DELAY_US);
709 +
710 + /* Polling status */
711 + ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,
712 + PLL_READY_TX_BIT, COMPHY_PLL_SLEEP,
713 + COMPHY_PLL_TIMEOUT);
714 + if (ret) {
715 + dev_err(lane->dev, "Failed to lock SATA PLL\n");
716 + return ret;
717 + }
718 +
719 + return 0;
720 +}
721 +
722 +static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
723 + bool is_1gbps)
724 +{
725 + int addr, fix_idx;
726 + u16 val;
727 +
728 + fix_idx = 0;
729 + for (addr = 0; addr < 512; addr++) {
730 + /*
731 + * All PHY register values are defined in full for 3.125Gbps
732 + * SERDES speed. The values required for 1.25 Gbps are almost
733 + * the same and only few registers should be "fixed" in
734 + * comparison to 3.125 Gbps values. These register values are
735 + * stored in "gbe_phy_init_fix" array.
736 + */
737 + if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {
738 + /* Use new value */
739 + val = gbe_phy_init_fix[fix_idx].value;
740 + if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))
741 + fix_idx++;
742 + } else {
743 + val = gbe_phy_init[addr];
744 + }
745 +
746 + comphy_lane_reg_set(lane, addr, val, 0xFFFF);
747 + }
748 +}
749 +
750 +static int
751 +mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)
752 +{
753 + u32 mask, data, speed_sel;
754 + int ret;
755 +
756 + /* Set selector */
757 + ret = mvebu_a3700_comphy_set_phy_selector(lane);
758 + if (ret)
759 + return ret;
760 +
761 + /*
762 + * 1. Reset PHY by setting PHY input port PIN_RESET=1.
763 + * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
764 + * PHY TXP/TXN output to idle state during PHY initialization
765 + * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
766 + */
767 + data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
768 + mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
769 + PIN_PU_TX_BIT | PHY_RX_INIT_BIT;
770 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
771 +
772 + /* 4. Release reset to the PHY by setting PIN_RESET=0. */
773 + data = 0x0;
774 + mask = PIN_RESET_COMPHY_BIT;
775 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
776 +
777 + /*
778 + * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY
779 + * bit rate
780 + */
781 + switch (lane->submode) {
782 + case PHY_INTERFACE_MODE_SGMII:
783 + case PHY_INTERFACE_MODE_1000BASEX:
784 + /* SGMII 1G, SerDes speed 1.25G */
785 + speed_sel = SERDES_SPEED_1_25_G;
786 + break;
787 + case PHY_INTERFACE_MODE_2500BASEX:
788 + /* 2500Base-X, SerDes speed 3.125G */
789 + speed_sel = SERDES_SPEED_3_125_G;
790 + break;
791 default:
792 + /* Other rates are not supported */
793 + dev_err(lane->dev,
794 + "unsupported phy speed %d on comphy lane%d\n",
795 + lane->submode, lane->id);
796 return -EINVAL;
797 }
798 + data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel);
799 + mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;
800 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
801 +
802 + /*
803 + * 6. Wait 10mS for bandgap and reference clocks to stabilize; then
804 + * start SW programming.
805 + */
806 + mdelay(10);
807 +
808 + /* 7. Program COMPHY register PHY_MODE */
809 + data = COMPHY_MODE_SERDES;
810 + mask = COMPHY_MODE_MASK;
811 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
812 +
813 + /*
814 + * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK
815 + * source
816 + */
817 + data = 0x0;
818 + mask = PHY_REF_CLK_SEL;
819 + comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
820 +
821 + /*
822 + * 9. Set correct reference clock frequency in COMPHY register
823 + * REF_FREF_SEL.
824 + */
825 + if (lane->priv->xtal_is_40m)
826 + data = REF_FREF_SEL_SERDES_50MHZ;
827 + else
828 + data = REF_FREF_SEL_SERDES_25MHZ;
829 +
830 + mask = REF_FREF_SEL_MASK;
831 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
832 +
833 + /* 10. Program COMPHY register PHY_GEN_MAX[1:0]
834 + * This step is mentioned in the flow received from verification team.
835 + * However the PHY_GEN_MAX value is only meaningful for other interfaces
836 + * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or
837 + * PCIe speed 2.5/5 Gbps
838 + */
839 +
840 + /*
841 + * 11. Program COMPHY register SEL_BITS to set correct parallel data
842 + * bus width
843 + */
844 + data = DATA_WIDTH_10BIT;
845 + mask = SEL_DATA_WIDTH_MASK;
846 + comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);
847 +
848 + /*
849 + * 12. As long as DFE function needs to be enabled in any mode,
850 + * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
851 + * for real chip during COMPHY power on.
852 + * The step 14 exists (and empty) in the original initialization flow
853 + * obtained from the verification team. According to the functional
854 + * specification DFE_UPDATE_EN already has the default value 0x3F
855 + */
856 +
857 + /*
858 + * 13. Program COMPHY GEN registers.
859 + * These registers should be programmed based on the lab testing result
860 + * to achieve optimal performance. Please contact the CEA group to get
861 + * the related GEN table during real chip bring-up. We only required to
862 + * run though the entire registers programming flow defined by
863 + * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock
864 + * 25 MHz the default values stored in PHY registers are OK.
865 + */
866 + dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n",
867 + lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G");
868 + if (lane->priv->xtal_is_40m)
869 + comphy_gbe_phy_init(lane,
870 + lane->submode != PHY_INTERFACE_MODE_2500BASEX);
871 +
872 + /*
873 + * 14. [Simulation Only] should not be used for real chip.
874 + * By pass power up calibration by programming EXT_FORCE_CAL_DONE
875 + * (R02h[9]) to 1 to shorten COMPHY simulation time.
876 + */
877 +
878 + /*
879 + * 15. [Simulation Only: should not be used for real chip]
880 + * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training
881 + * simulation time.
882 + */
883 +
884 + /*
885 + * 16. Check the PHY Polarity invert bit
886 + */
887 + data = 0x0;
888 + if (lane->invert_tx)
889 + data |= TXD_INVERT_BIT;
890 + if (lane->invert_rx)
891 + data |= RXD_INVERT_BIT;
892 + mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
893 + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
894 +
895 + /*
896 + * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
897 + * start PHY power up sequence. All the PHY register programming should
898 + * be done before PIN_PU_PLL=1. There should be no register programming
899 + * for normal PHY operation from this point.
900 + */
901 + data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
902 + mask = data;
903 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
904 +
905 + /*
906 + * 18. Wait for PHY power up sequence to finish by checking output ports
907 + * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
908 + */
909 + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
910 + PHY_PLL_READY_TX_BIT |
911 + PHY_PLL_READY_RX_BIT,
912 + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
913 + if (ret) {
914 + dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
915 + lane->id);
916 + return ret;
917 + }
918 +
919 + /*
920 + * 19. Set COMPHY input port PIN_TX_IDLE=0
921 + */
922 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);
923 +
924 + /*
925 + * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
926 + * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
927 + * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
928 + * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
929 + * refer to RX initialization part for details.
930 + */
931 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1,
932 + PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
933 +
934 + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
935 + PHY_PLL_READY_TX_BIT |
936 + PHY_PLL_READY_RX_BIT,
937 + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
938 + if (ret) {
939 + dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
940 + lane->id);
941 + return ret;
942 + }
943 +
944 + ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
945 + PHY_RX_INIT_DONE_BIT,
946 + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
947 + if (ret) {
948 + dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n",
949 + lane->id);
950 + return ret;
951 + }
952 +
953 + return 0;
954 +}
955 +
956 +static int
957 +mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)
958 +{
959 + u32 mask, data, cfg, ref_clk;
960 + int ret;
961 +
962 + /* Set phy seclector */
963 + ret = mvebu_a3700_comphy_set_phy_selector(lane);
964 + if (ret)
965 + return ret;
966 +
967 + /*
968 + * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
969 + * register belong to UTMI module, so it is set in UTMI phy driver.
970 + */
971 +
972 + /*
973 + * 1. Set PRD_TXDEEMPH (3.5db de-emph)
974 + */
975 + data = PRD_TXDEEMPH0_MASK;
976 + mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
977 + CFG_TX_ALIGN_POS_MASK;
978 + comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);
979 +
980 + /*
981 + * 2. Set BIT0: enable transmitter in high impedance mode
982 + * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
983 + * Set BIT6: Tx detect Rx at HiZ mode
984 + * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
985 + * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register
986 + */
987 + data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
988 + mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
989 + TX_ELEC_IDLE_MODE_EN;
990 + comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);
991 +
992 + /*
993 + * 3. Set Spread Spectrum Clock Enabled
994 + */
995 + comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,
996 + SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
997 +
998 + /*
999 + * 4. Set Override Margining Controls From the MAC:
1000 + * Use margining signals from lane configuration
1001 + */
1002 + comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,
1003 + MODE_MARGIN_OVERRIDE, 0xFFFF);
1004 +
1005 + /*
1006 + * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
1007 + * set Mode Clock Source = PCLK is generated from REFCLK
1008 + */
1009 + data = 0x0;
1010 + mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK |
1011 + BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK;
1012 + comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);
1013 +
1014 + /*
1015 + * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
1016 + */
1017 + comphy_lane_reg_set(lane, COMPHY_GEN2_SET2,
1018 + GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK);
1019 +
1020 + /*
1021 + * 7. Unset G3 Spread Spectrum Clock Amplitude
1022 + * set G3 TX and RX Register Master Current Select
1023 + */
1024 + data = GS2_VREG_RXTX_MAS_ISET_60U;
1025 + mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |
1026 + GS2_RSVD_6_0_MASK;
1027 + comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);
1028 +
1029 + /*
1030 + * 8. Check crystal jumper setting and program the Power and PLL Control
1031 + * accordingly Change RX wait
1032 + */
1033 + if (lane->priv->xtal_is_40m) {
1034 + ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
1035 + cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
1036 + } else {
1037 + ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
1038 + cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
1039 + }
1040 +
1041 + data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1042 + PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk;
1043 + mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1044 + PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK |
1045 + REF_FREF_SEL_MASK;
1046 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1047 +
1048 + data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
1049 + mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
1050 + CFG_PM_RXDLOZ_WAIT_MASK;
1051 + comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1052 +
1053 + /*
1054 + * 9. Enable idle sync
1055 + */
1056 + comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
1057 + IDLE_SYNC_EN, IDLE_SYNC_EN);
1058 +
1059 + /*
1060 + * 10. Enable the output of 500M clock
1061 + */
1062 + comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);
1063 +
1064 + /*
1065 + * 11. Set 20-bit data width
1066 + */
1067 + comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
1068 + DATA_WIDTH_20BIT, 0xFFFF);
1069 +
1070 + /*
1071 + * 12. Override Speed_PLL value and use MAC PLL
1072 + */
1073 + data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT;
1074 + mask = 0xFFFF;
1075 + comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);
1076 +
1077 + /*
1078 + * 13. Check the Polarity invert bit
1079 + */
1080 + data = 0x0;
1081 + if (lane->invert_tx)
1082 + data |= TXD_INVERT_BIT;
1083 + if (lane->invert_rx)
1084 + data |= RXD_INVERT_BIT;
1085 + mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
1086 + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1087 +
1088 + /*
1089 + * 14. Set max speed generation to USB3.0 5Gbps
1090 + */
1091 + comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,
1092 + PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK);
1093 +
1094 + /*
1095 + * 15. Set capacitor value for FFE gain peaking to 0xF
1096 + */
1097 + comphy_lane_reg_set(lane, COMPHY_GEN2_SET3,
1098 + GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);
1099 +
1100 + /*
1101 + * 16. Release SW reset
1102 + */
1103 + data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
1104 + mask = 0xFFFF;
1105 + comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1106 +
1107 + /* Wait for > 55 us to allow PCLK be enabled */
1108 + udelay(PLL_SET_DELAY_US);
1109 +
1110 + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
1111 + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
1112 + if (ret) {
1113 + dev_err(lane->dev, "Failed to lock USB3 PLL\n");
1114 + return ret;
1115 + }
1116 +
1117 + return 0;
1118 +}
1119 +
1120 +static int
1121 +mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)
1122 +{
1123 + u32 mask, data, ref_clk;
1124 + int ret;
1125 +
1126 + /* Configure phy selector for PCIe */
1127 + ret = mvebu_a3700_comphy_set_phy_selector(lane);
1128 + if (ret)
1129 + return ret;
1130 +
1131 + /* 1. Enable max PLL. */
1132 + comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,
1133 + USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
1134 +
1135 + /* 2. Select 20 bit SERDES interface. */
1136 + comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,
1137 + CFG_SEL_20B, CFG_SEL_20B);
1138 +
1139 + /* 3. Force to use reg setting for PCIe mode */
1140 + comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,
1141 + SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
1142 +
1143 + /* 4. Change RX wait */
1144 + data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT;
1145 + mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
1146 + CFG_PM_RXDLOZ_WAIT_MASK;
1147 + comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1148 +
1149 + /* 5. Enable idle sync */
1150 + comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
1151 + IDLE_SYNC_EN, IDLE_SYNC_EN);
1152 +
1153 + /* 6. Enable the output of 100M/125M/500M clock */
1154 + data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN;
1155 + mask = data;
1156 + comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
1157 +
1158 + /*
1159 + * 7. Enable TX, PCIE global register, 0xd0074814, it is done in
1160 + * PCI-E driver
1161 + */
1162 +
1163 + /*
1164 + * 8. Check crystal jumper setting and program the Power and PLL
1165 + * Control accordingly
1166 + */
1167 +
1168 + if (lane->priv->xtal_is_40m)
1169 + ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
1170 + else
1171 + ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
1172 +
1173 + data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1174 + PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk;
1175 + mask = 0xFFFF;
1176 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1177 +
1178 + /* 9. Override Speed_PLL value and use MAC PLL */
1179 + comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
1180 + SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT,
1181 + 0xFFFF);
1182 +
1183 + /* 10. Check the Polarity invert bit */
1184 + data = 0x0;
1185 + if (lane->invert_tx)
1186 + data |= TXD_INVERT_BIT;
1187 + if (lane->invert_rx)
1188 + data |= RXD_INVERT_BIT;
1189 + mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
1190 + comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1191 +
1192 + /* 11. Release SW reset */
1193 + data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
1194 + mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;
1195 + comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1196 +
1197 + /* Wait for > 55 us to allow PCLK be enabled */
1198 + udelay(PLL_SET_DELAY_US);
1199 +
1200 + ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
1201 + COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
1202 + if (ret) {
1203 + dev_err(lane->dev, "Failed to lock PCIE PLL\n");
1204 + return ret;
1205 + }
1206 +
1207 + return 0;
1208 +}
1209 +
1210 +static void
1211 +mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
1212 +{
1213 + /*
1214 + * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not
1215 + * need to power off USB3 PHY again.
1216 + */
1217 +}
1218 +
1219 +static void
1220 +mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)
1221 +{
1222 + /* Set phy isolation mode */
1223 + comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
1224 + PHY_ISOLATE_MODE, PHY_ISOLATE_MODE);
1225 +
1226 + /* Power off PLL, Tx, Rx */
1227 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1228 + 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
1229 +}
1230 +
1231 +static void
1232 +mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)
1233 +{
1234 + u32 mask, data;
1235 +
1236 + data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT |
1237 + PHY_RX_INIT_BIT;
1238 + mask = data;
1239 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
1240 +}
1241 +
1242 +static void
1243 +mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)
1244 +{
1245 + /* Power off PLL, Tx, Rx */
1246 + comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1247 + 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
1248 +}
1249 +
1250 +static int mvebu_a3700_comphy_reset(struct phy *phy)
1251 +{
1252 + struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1253 + u16 mask, data;
1254 +
1255 + dev_dbg(lane->dev, "resetting lane %d\n", lane->id);
1256 +
1257 + /* COMPHY reset for internal logic */
1258 + comphy_lane_reg_set(lane, COMPHY_SFT_RESET,
1259 + SFT_RST_NO_REG, SFT_RST_NO_REG);
1260 +
1261 + /* COMPHY register reset (cleared automatically) */
1262 + comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
1263 +
1264 + /* PIPE soft and register reset */
1265 + data = PIPE_SOFT_RESET | PIPE_REG_RESET;
1266 + mask = data;
1267 + comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1268 +
1269 + /* Release PIPE register reset */
1270 + comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,
1271 + 0x0, PIPE_REG_RESET);
1272 +
1273 + /* Reset SB configuration register (only for lanes 0 and 1) */
1274 + if (lane->id == 0 || lane->id == 1) {
1275 + u32 mask, data;
1276 +
1277 + data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |
1278 + PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
1279 + mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;
1280 + comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
1281 + }
1282 +
1283 + return 0;
1284 }
1285
1286 -static int mvebu_a3700_comphy_get_fw_mode(int lane,
1287 +static bool mvebu_a3700_comphy_check_mode(int lane,
1288 enum phy_mode mode,
1289 int submode)
1290 {
1291 @@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mode(int lane,
1292
1293 /* Unused PHY mux value is 0x0 */
1294 if (mode == PHY_MODE_INVALID)
1295 - return -EINVAL;
1296 + return false;
1297
1298 for (i = 0; i < n; i++) {
1299 if (mvebu_a3700_comphy_modes[i].lane == lane &&
1300 @@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mode(int lane,
1301 }
1302
1303 if (i == n)
1304 - return -EINVAL;
1305 + return false;
1306
1307 - return mvebu_a3700_comphy_modes[i].fw_mode;
1308 + return true;
1309 }
1310
1311 static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
1312 int submode)
1313 {
1314 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1315 - int fw_mode;
1316 -
1317 - if (submode == PHY_INTERFACE_MODE_1000BASEX)
1318 - submode = PHY_INTERFACE_MODE_SGMII;
1319
1320 - fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,
1321 - submode);
1322 - if (fw_mode < 0) {
1323 + if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {
1324 dev_err(lane->dev, "invalid COMPHY mode\n");
1325 - return fw_mode;
1326 + return -EINVAL;
1327 }
1328
1329 + /* Mode cannot be changed while the PHY is powered on */
1330 + if (phy->power_count &&
1331 + (lane->mode != mode || lane->submode != submode))
1332 + return -EBUSY;
1333 +
1334 + /* If changing mode, ensure reset is called */
1335 + if (lane->mode != PHY_MODE_INVALID && lane->mode != mode)
1336 + lane->needs_reset = true;
1337 +
1338 /* Just remember the mode, ->power_on() will do the real setup */
1339 lane->mode = mode;
1340 lane->submode = submode;
1341 @@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
1342 static int mvebu_a3700_comphy_power_on(struct phy *phy)
1343 {
1344 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1345 - u32 fw_param;
1346 - int fw_mode;
1347 - int fw_port;
1348 int ret;
1349
1350 - fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,
1351 - lane->mode, lane->submode);
1352 - if (fw_mode < 0) {
1353 + if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,
1354 + lane->submode)) {
1355 dev_err(lane->dev, "invalid COMPHY mode\n");
1356 - return fw_mode;
1357 + return -EINVAL;
1358 + }
1359 +
1360 + if (lane->needs_reset) {
1361 + ret = mvebu_a3700_comphy_reset(phy);
1362 + if (ret)
1363 + return ret;
1364 +
1365 + lane->needs_reset = false;
1366 }
1367
1368 switch (lane->mode) {
1369 case PHY_MODE_USB_HOST_SS:
1370 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
1371 - fw_param = COMPHY_FW_MODE(fw_mode);
1372 - break;
1373 + return mvebu_a3700_comphy_usb3_power_on(lane);
1374 case PHY_MODE_SATA:
1375 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
1376 - fw_param = COMPHY_FW_MODE(fw_mode);
1377 - break;
1378 + return mvebu_a3700_comphy_sata_power_on(lane);
1379 case PHY_MODE_ETHERNET:
1380 - fw_port = (lane->id == 0) ? 1 : 0;
1381 - switch (lane->submode) {
1382 - case PHY_INTERFACE_MODE_SGMII:
1383 - dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
1384 - lane->id);
1385 - fw_param = COMPHY_FW_NET(fw_mode, fw_port,
1386 - COMPHY_FW_SPEED_1_25G);
1387 - break;
1388 - case PHY_INTERFACE_MODE_2500BASEX:
1389 - dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
1390 - lane->id);
1391 - fw_param = COMPHY_FW_NET(fw_mode, fw_port,
1392 - COMPHY_FW_SPEED_3_125G);
1393 - break;
1394 - default:
1395 - dev_err(lane->dev, "unsupported PHY submode (%d)\n",
1396 - lane->submode);
1397 - return -ENOTSUPP;
1398 - }
1399 - break;
1400 + dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id);
1401 + return mvebu_a3700_comphy_ethernet_power_on(lane);
1402 case PHY_MODE_PCIE:
1403 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
1404 - fw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,
1405 - phy->attrs.bus_width);
1406 - break;
1407 + return mvebu_a3700_comphy_pcie_power_on(lane);
1408 default:
1409 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
1410 - return -ENOTSUPP;
1411 + return -EOPNOTSUPP;
1412 }
1413 -
1414 - ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
1415 - if (ret == -EOPNOTSUPP)
1416 - dev_err(lane->dev,
1417 - "unsupported SMC call, try updating your firmware\n");
1418 -
1419 - return ret;
1420 }
1421
1422 static int mvebu_a3700_comphy_power_off(struct phy *phy)
1423 {
1424 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1425
1426 - return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
1427 + switch (lane->mode) {
1428 + case PHY_MODE_USB_HOST_SS:
1429 + mvebu_a3700_comphy_usb3_power_off(lane);
1430 + return 0;
1431 + case PHY_MODE_SATA:
1432 + mvebu_a3700_comphy_sata_power_off(lane);
1433 + return 0;
1434 + case PHY_MODE_ETHERNET:
1435 + mvebu_a3700_comphy_ethernet_power_off(lane);
1436 + return 0;
1437 + case PHY_MODE_PCIE:
1438 + mvebu_a3700_comphy_pcie_power_off(lane);
1439 + return 0;
1440 + default:
1441 + dev_err(lane->dev, "invalid COMPHY mode\n");
1442 + return -EINVAL;
1443 + }
1444 }
1445
1446 static const struct phy_ops mvebu_a3700_comphy_ops = {
1447 .power_on = mvebu_a3700_comphy_power_on,
1448 .power_off = mvebu_a3700_comphy_power_off,
1449 + .reset = mvebu_a3700_comphy_reset,
1450 .set_mode = mvebu_a3700_comphy_set_mode,
1451 .owner = THIS_MODULE,
1452 };
1453 @@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
1454 return ERR_PTR(-EINVAL);
1455 }
1456
1457 + lane->invert_tx = args->args[1] & BIT(0);
1458 + lane->invert_rx = args->args[1] & BIT(1);
1459 +
1460 return phy;
1461 }
1462
1463 static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
1464 {
1465 + struct mvebu_a3700_comphy_priv *priv;
1466 struct phy_provider *provider;
1467 struct device_node *child;
1468 + struct resource *res;
1469 + struct clk *clk;
1470 + int ret;
1471 +
1472 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1473 + if (!priv)
1474 + return -ENOMEM;
1475 +
1476 + spin_lock_init(&priv->lock);
1477 +
1478 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy");
1479 + priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res);
1480 + if (IS_ERR(priv->comphy_regs))
1481 + return PTR_ERR(priv->comphy_regs);
1482 +
1483 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1484 + "lane1_pcie_gbe");
1485 + priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res);
1486 + if (IS_ERR(priv->lane1_phy_regs))
1487 + return PTR_ERR(priv->lane1_phy_regs);
1488 +
1489 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1490 + "lane0_usb3_gbe");
1491 + priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res);
1492 + if (IS_ERR(priv->lane0_phy_regs))
1493 + return PTR_ERR(priv->lane0_phy_regs);
1494 +
1495 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1496 + "lane2_sata_usb3");
1497 + priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res);
1498 + if (IS_ERR(priv->lane2_phy_indirect))
1499 + return PTR_ERR(priv->lane2_phy_indirect);
1500 +
1501 + /*
1502 + * Driver needs to know if reference xtal clock is 40MHz or 25MHz.
1503 + * Old DT bindings do not have xtal clk present. So do not fail here
1504 + * and expects that default 25MHz reference clock is used.
1505 + */
1506 + clk = clk_get(&pdev->dev, "xtal");
1507 + if (IS_ERR(clk)) {
1508 + if (PTR_ERR(clk) == -EPROBE_DEFER)
1509 + return -EPROBE_DEFER;
1510 + dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n",
1511 + PTR_ERR(clk));
1512 + } else {
1513 + ret = clk_prepare_enable(clk);
1514 + if (ret) {
1515 + dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n",
1516 + ret);
1517 + } else {
1518 + if (clk_get_rate(clk) == 40000000)
1519 + priv->xtal_is_40m = true;
1520 + clk_disable_unprepare(clk);
1521 + }
1522 + clk_put(clk);
1523 + }
1524 +
1525 + dev_set_drvdata(&pdev->dev, priv);
1526
1527 for_each_available_child_of_node(pdev->dev.of_node, child) {
1528 struct mvebu_a3700_comphy_lane *lane;
1529 @@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
1530 continue;
1531 }
1532
1533 - if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
1534 + if (lane_id >= 3) {
1535 dev_err(&pdev->dev, "invalid 'reg' property\n");
1536 continue;
1537 }
1538 @@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
1539 return PTR_ERR(phy);
1540 }
1541
1542 + lane->priv = priv;
1543 lane->dev = &pdev->dev;
1544 lane->mode = PHY_MODE_INVALID;
1545 lane->submode = PHY_INTERFACE_MODE_NA;
1546 lane->id = lane_id;
1547 + lane->invert_tx = false;
1548 + lane->invert_rx = false;
1549 phy_set_drvdata(phy, lane);
1550 +
1551 + /*
1552 + * To avoid relying on the bootloader/firmware configuration,
1553 + * power off all comphys.
1554 + */
1555 + mvebu_a3700_comphy_reset(phy);
1556 + lane->needs_reset = false;
1557 }
1558
1559 provider = devm_of_phy_provider_register(&pdev->dev,
1560 @@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a3700_comphy_driver = {
1561 module_platform_driver(mvebu_a3700_comphy_driver);
1562
1563 MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
1564 +MODULE_AUTHOR("Pali Rohár <pali@kernel.org>");
1565 +MODULE_AUTHOR("Marek Behún <kabel@kernel.org>");
1566 MODULE_DESCRIPTION("Common PHY driver for A3700");
1567 MODULE_LICENSE("GPL v2");
1568 --
1569 2.34.1
1570
Hauke Mehrtens staging tree