git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From b70caff0f9592719b6c977e291c33192e959c9d4 Mon Sep 17 00:00:00 2001
   2 From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
   3 Date: Thu, 29 Aug 2024 14:26:57 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add IR-receiver to NanoPC-T6
   5
   6 FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line
   7 which ends as GPIO0_D4.
   8
   9 Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  10 Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-6-edff247e8c02@linaro.org
  11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  12 ---
  13  .../arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++++++-
  14  1 file changed, 14 insertions(+), 1 deletion(-)
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
  18 @@ -25,6 +25,13 @@
  19                 stdout-path = "serial2:1500000n8";
  20         };
  21
  22 +       ir-receiver {
  23 +               compatible = "gpio-ir-receiver";
  24 +               gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
  25 +               pinctrl-names = "default";
  26 +               pinctrl-0 = <&ir_receiver_pin>;
  27 +       };
  28 +
  29         leds {
  30                 compatible = "gpio-leds";
  31
  32 @@ -228,7 +235,7 @@
  33                           "HEADER_10", "HEADER_08", "HEADER_32", "",
  34                           /* GPIO0 D0-D7 */
  35                           "", "", "", "",
  36 -                         "", "", "", "";
  37 +                         "IR receiver [PWM3_IR_M0]", "", "", "";
  38  };
  39
  40  &gpio1 {
  41 @@ -492,6 +499,12 @@
  42                 };
  43         };
  44
  45 +       ir-receiver {
  46 +               ir_receiver_pin: ir-receiver-pin {
  47 +                       rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
  48 +               };
  49 +       };
  50 +
  51         pcie {
  52                 pcie2_0_rst: pcie2-0-rst {
  53                         rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;