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1 From 794b9e55c77bf0ef34dfdb3b151a845c004b3ce3 Mon Sep 17 00:00:00 2001
2 From: Li Yang <leoyang.li@nxp.com>
3 Date: Thu, 2 May 2019 16:01:01 -0500
4 Subject: [PATCH] arm64: dts: ls1043a: accumulated change for ls1043a boards
5
6 commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
7 Author: Peng Ma <peng.ma@nxp.com>
8 Date: Wed Jul 25 08:53:07 2018 +0000
9
10 dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
11 support
12
13 add block-offset to support different virtual block offset for qdma
14 base on soc;
15 the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
16 block,N based on block number of qdma;
17
18 Signed-off-by: Peng Ma <peng.ma@nxp.com>
19
20 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
21 Date: Mon Apr 2 16:22:40 2018 +0800
22
23 arm64: dts: ls1043a: add dts entry for A-010650
24
25 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
26
27 commit a47e4bd0b5d076feb6d81601c16d5b79e53a92c8
28 Author: Rajesh Bhagat <rajesh.bhagat@freescale.com>
29 Date: Wed Jan 27 11:37:25 2016 +0530
30
31 arm64: dts: ls1043a: Add configure-gfladj property to USB3 node
32
33 Add "configure-gfladj" boolean property to USB3 node. This property
34 is used to determine whether frame length adjustent is required
35 or not
36
37 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
38 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
39
40 commit 38566bbd5ca6747b30d2f0c251bbcfe0723df8c6
41 Author: Changming Huang <jerry.huang@nxp.com>
42 Date: Wed Apr 19 12:49:50 2017 +0800
43
44 arm/arm64: dts: Add property snps incr burst type adjustment for
45 INCR burst type for dwc3
46
47 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
48 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
49
50 commit 8632d84e0fe187aa023a24f0dad0040c53e12450
51 Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
52 Date: Thu Jan 25 11:31:13 2018 +0530
53
54 arm64: dts: freescale: ls1043a: Modify DT nodes for qspi
55
56 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
57
58 commit b1dc1ebed79e9aaab75fd06837d794ec2f1b624d
59 Author: Ran Wang <ran.wang_1@nxp.com>
60 Date: Fri Jan 5 15:14:48 2018 +0800
61
62 arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node
63
64 Enable USB3 HW LPM feature for ls1043a and active patch for
65 snps erratum A-010131. It will disable U1/U2 temperary when
66 initiate U3 request.
67
68 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
69
70 commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
71 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
72 Date: Tue Jun 13 13:14:26 2017 +0800
73
74 arm64: dts: correct the register range of dcfg
75
76 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
77
78 commit f60e39fd51ad702e3a2613faaca40871a4763735
79 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
80 Date: Tue Aug 22 18:04:02 2017 +0800
81
82 arm64: dts: ls1043a: add pcf85263 rtc nodes
83
84 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
85
86 commit 67c82e3c7b376139d7cee624589bedbc311f8868
87 Author: jiaheng.fan <jiaheng.fan@nxp.com>
88 Date: Thu May 11 17:36:33 2017 +0800
89
90 arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
91 Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
92
93 commit c6d9c2498ee83669f9853100301edff9a5905caf
94 Author: Wang Dongsheng <dongsheng.wang@nxp.com>
95 Date: Fri Apr 21 13:26:07 2017 +0800
96
97 arm64: dts: ls1043a: add ftm0 nodes
98
99 Add rcpm and ftm0 nodes. The Power Management related features
100 need these nodes.
101
102 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
103
104 commit 3bcdc4de0a1c9e6f4a4ddc916e8efe8044d8bbfd
105 Author: Po Liu <po.liu@nxp.com>
106 Date: Fri Sep 30 17:11:36 2016 +0800
107
108 arm64: dts: ls1043/ls2080: add pcie aer/pme interrupt-name property
109
110 Some platforms(NXP Layerscape for example) aer/pme interrupts was
111 not
112 MSI/MSI-X/INTx but using interrupt line independently. This patch
113 add "aer", "pme" interrupt-names for aer/pme interrupt.
114
115 With the interrupt-names "aer", "pme" code could probe aer/pme
116 interrupt
117 line for pcie root port, replace the aer/pme interrupt service irqs.
118
119 This is intend to fixup the Layerscape platforms which aer/pmes
120 interrupts
121 was not MSI/MSI-X/INTx, but using interrupt line independently.
122
123 Since the interrupt-names "intr" never been used. Remove it.
124
125 Signed-off-by: Po Liu <po.liu@nxp.com>
126 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
127
128 commit 4d20ecf029f1255520b30c103e1724c618b981c7
129 Author: Zhao Qiang <qiang.zhao@nxp.com>
130 Date: Sun Jun 12 15:51:44 2016 +0800
131
132 arm64: dts: ls1043ardb: add ds26522 node
133
134 add ds26522 node to fsl-ls1043a-rdb.dts
135
136 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
137
138 commit ca470562646ab058814fc4a1195016fb3266cdf5
139 Author: Zhao Qiang <qiang.zhao@nxp.com>
140 Date: Sun Jun 12 15:44:11 2016 +0800
141
142 arm64: dts: ls1043ardb: add qe node
143
144 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
145 ---
146 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 162 ++++++++++++++++++++++
147 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 36 +++++
148 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 108 +++++++++++++--
149 3 files changed, 295 insertions(+), 11 deletions(-)
150
151 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
152 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
153 @@ -24,6 +24,22 @@
154 serial1 = &duart1;
155 serial2 = &duart2;
156 serial3 = &duart3;
157 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
158 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
159 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
160 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
161 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
162 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
163 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
164 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
165 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
166 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
167 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
168 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
169 + emi1_slot1 = &ls1043mdio_s1;
170 + emi1_slot2 = &ls1043mdio_s2;
171 + emi1_slot3 = &ls1043mdio_s3;
172 + emi1_slot4 = &ls1043mdio_s4;
173 };
174
175 chosen {
176 @@ -64,6 +80,8 @@
177 fpga: board-control@2,0 {
178 compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
179 reg = <0x2 0x0 0x0000100>;
180 + #address-cells = <1>;
181 + #size-cells = <1>;
182 };
183 };
184
185 @@ -149,3 +167,147 @@
186 };
187
188 #include "fsl-ls1043-post.dtsi"
189 +
190 +&fman0 {
191 + ethernet@e0000 {
192 + phy-handle = <&qsgmii_phy_s2_p1>;
193 + phy-connection-type = "sgmii";
194 + };
195 +
196 + ethernet@e2000 {
197 + phy-handle = <&qsgmii_phy_s2_p2>;
198 + phy-connection-type = "sgmii";
199 + };
200 +
201 + ethernet@e4000 {
202 + phy-handle = <&rgmii_phy1>;
203 + phy-connection-type = "rgmii";
204 + };
205 +
206 + ethernet@e6000 {
207 + phy-handle = <&rgmii_phy2>;
208 + phy-connection-type = "rgmii";
209 + };
210 +
211 + ethernet@e8000 {
212 + phy-handle = <&qsgmii_phy_s2_p3>;
213 + phy-connection-type = "sgmii";
214 + };
215 +
216 + ethernet@ea000 {
217 + phy-handle = <&qsgmii_phy_s2_p4>;
218 + phy-connection-type = "sgmii";
219 + };
220 +
221 + ethernet@f0000 { /* DTSEC9/10GEC1 */
222 + fixed-link = <1 1 10000 0 0>;
223 + phy-connection-type = "xgmii";
224 + };
225 +};
226 +
227 +&fpga {
228 + mdio-mux-emi1 {
229 + compatible = "mdio-mux-mmioreg", "mdio-mux";
230 + mdio-parent-bus = <&mdio0>;
231 + #address-cells = <1>;
232 + #size-cells = <0>;
233 + reg = <0x54 1>; /* BRDCFG4 */
234 + mux-mask = <0xe0>; /* EMI1 */
235 +
236 + /* On-board RGMII1 PHY */
237 + ls1043mdio0: mdio@0 {
238 + reg = <0>;
239 + #address-cells = <1>;
240 + #size-cells = <0>;
241 +
242 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
243 + reg = <0x1>;
244 + };
245 + };
246 +
247 + /* On-board RGMII2 PHY */
248 + ls1043mdio1: mdio@1 {
249 + reg = <0x20>;
250 + #address-cells = <1>;
251 + #size-cells = <0>;
252 +
253 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
254 + reg = <0x2>;
255 + };
256 + };
257 +
258 + /* Slot 1 */
259 + ls1043mdio_s1: mdio@2 {
260 + reg = <0x40>;
261 + #address-cells = <1>;
262 + #size-cells = <0>;
263 + status = "disabled";
264 +
265 + qsgmii_phy_s1_p1: ethernet-phy@4 {
266 + reg = <0x4>;
267 + };
268 + qsgmii_phy_s1_p2: ethernet-phy@5 {
269 + reg = <0x5>;
270 + };
271 + qsgmii_phy_s1_p3: ethernet-phy@6 {
272 + reg = <0x6>;
273 + };
274 + qsgmii_phy_s1_p4: ethernet-phy@7 {
275 + reg = <0x7>;
276 + };
277 +
278 + sgmii_phy_s1_p1: ethernet-phy@1c {
279 + reg = <0x1c>;
280 + };
281 + };
282 +
283 + /* Slot 2 */
284 + ls1043mdio_s2: mdio@3 {
285 + reg = <0x60>;
286 + #address-cells = <1>;
287 + #size-cells = <0>;
288 + status = "disabled";
289 +
290 + qsgmii_phy_s2_p1: ethernet-phy@8 {
291 + reg = <0x8>;
292 + };
293 + qsgmii_phy_s2_p2: ethernet-phy@9 {
294 + reg = <0x9>;
295 + };
296 + qsgmii_phy_s2_p3: ethernet-phy@a {
297 + reg = <0xa>;
298 + };
299 + qsgmii_phy_s2_p4: ethernet-phy@b {
300 + reg = <0xb>;
301 + };
302 +
303 + sgmii_phy_s2_p1: ethernet-phy@1c {
304 + reg = <0x1c>;
305 + };
306 + };
307 +
308 + /* Slot 3 */
309 + ls1043mdio_s3: mdio@4 {
310 + reg = <0x80>;
311 + #address-cells = <1>;
312 + #size-cells = <0>;
313 + status = "disabled";
314 +
315 + sgmii_phy_s3_p1: ethernet-phy@1c {
316 + reg = <0x1c>;
317 + };
318 + };
319 +
320 + /* Slot 4 */
321 + ls1043mdio_s4: mdio@5 {
322 + reg = <0xa0>;
323 + #address-cells = <1>;
324 + #size-cells = <0>;
325 + status = "disabled";
326 +
327 + sgmii_phy_s4_p1: ethernet-phy@1c {
328 + reg = <0x1c>;
329 + };
330 + };
331 + };
332 +};
333 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
334 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
335 @@ -49,6 +49,10 @@
336 compatible = "pericom,pt7c4338";
337 reg = <0x68>;
338 };
339 + rtc@51 {
340 + compatible = "nxp,pcf85263";
341 + reg = <0x51>;
342 + };
343 };
344
345 &ifc {
346 @@ -94,6 +98,38 @@
347 reg = <0>;
348 spi-max-frequency = <1000000>; /* input clock */
349 };
350 +
351 + slic@2 {
352 + compatible = "maxim,ds26522";
353 + reg = <2>;
354 + spi-max-frequency = <2000000>;
355 + fsl,spi-cs-sck-delay = <100>;
356 + fsl,spi-sck-cs-delay = <50>;
357 + };
358 +
359 + slic@3 {
360 + compatible = "maxim,ds26522";
361 + reg = <3>;
362 + spi-max-frequency = <2000000>;
363 + fsl,spi-cs-sck-delay = <100>;
364 + fsl,spi-sck-cs-delay = <50>;
365 + };
366 +};
367 +
368 +&uqe {
369 + ucc_hdlc: ucc@2000 {
370 + compatible = "fsl,ucc-hdlc";
371 + rx-clock-name = "clk8";
372 + tx-clock-name = "clk9";
373 + fsl,rx-sync-clock = "rsync_pin";
374 + fsl,tx-sync-clock = "tsync_pin";
375 + fsl,tx-timeslot-mask = <0xfffffffe>;
376 + fsl,rx-timeslot-mask = <0xfffffffe>;
377 + fsl,tdm-framer-type = "e1";
378 + fsl,tdm-id = <0>;
379 + fsl,siram-entry-id = <0>;
380 + fsl,tdm-interface;
381 + };
382 };
383
384 &duart0 {
385 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
386 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
387 @@ -277,7 +277,7 @@
388
389 dcfg: dcfg@1ee0000 {
390 compatible = "fsl,ls1043a-dcfg", "syscon";
391 - reg = <0x0 0x1ee0000 0x0 0x10000>;
392 + reg = <0x0 0x1ee0000 0x0 0x1000>;
393 big-endian;
394 };
395
396 @@ -411,7 +411,7 @@
397 };
398
399 i2c0: i2c@2180000 {
400 - compatible = "fsl,vf610-i2c";
401 + compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
402 #address-cells = <1>;
403 #size-cells = <0>;
404 reg = <0x0 0x2180000 0x0 0x10000>;
405 @@ -421,6 +421,7 @@
406 dmas = <&edma0 1 39>,
407 <&edma0 1 38>;
408 dma-names = "tx", "rx";
409 + scl-gpios = <&gpio4 12 0>;
410 status = "disabled";
411 };
412
413 @@ -525,6 +526,72 @@
414 #interrupt-cells = <2>;
415 };
416
417 + uqe: uqe@2400000 {
418 + #address-cells = <1>;
419 + #size-cells = <1>;
420 + device_type = "qe";
421 + compatible = "fsl,qe", "simple-bus";
422 + ranges = <0x0 0x0 0x2400000 0x40000>;
423 + reg = <0x0 0x2400000 0x0 0x480>;
424 + brg-frequency = <100000000>;
425 + bus-frequency = <200000000>;
426 +
427 + fsl,qe-num-riscs = <1>;
428 + fsl,qe-num-snums = <28>;
429 +
430 + qeic: qeic@80 {
431 + compatible = "fsl,qe-ic";
432 + reg = <0x80 0x80>;
433 + #address-cells = <0>;
434 + interrupt-controller;
435 + #interrupt-cells = <1>;
436 + interrupts = <0 77 0x04 0 77 0x04>;
437 + };
438 +
439 + si1: si@700 {
440 + #address-cells = <1>;
441 + #size-cells = <0>;
442 + compatible = "fsl,ls1043-qe-si",
443 + "fsl,t1040-qe-si";
444 + reg = <0x700 0x80>;
445 + };
446 +
447 + siram1: siram@1000 {
448 + #address-cells = <1>;
449 + #size-cells = <1>;
450 + compatible = "fsl,ls1043-qe-siram",
451 + "fsl,t1040-qe-siram";
452 + reg = <0x1000 0x800>;
453 + };
454 +
455 + ucc@2000 {
456 + cell-index = <1>;
457 + reg = <0x2000 0x200>;
458 + interrupts = <32>;
459 + interrupt-parent = <&qeic>;
460 + };
461 +
462 + ucc@2200 {
463 + cell-index = <3>;
464 + reg = <0x2200 0x200>;
465 + interrupts = <34>;
466 + interrupt-parent = <&qeic>;
467 + };
468 +
469 + muram@10000 {
470 + #address-cells = <1>;
471 + #size-cells = <1>;
472 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
473 + ranges = <0x0 0x10000 0x6000>;
474 +
475 + data-only@0 {
476 + compatible = "fsl,qe-muram-data",
477 + "fsl,cpm-muram-data";
478 + reg = <0x0 0x6000>;
479 + };
480 + };
481 + };
482 +
483 lpuart0: serial@2950000 {
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2950000 0x0 0x1000>;
486 @@ -579,6 +646,16 @@
487 status = "disabled";
488 };
489
490 + ftm0: ftm0@29d0000 {
491 + compatible = "fsl,ftm-alarm";
492 + reg = <0x0 0x29d0000 0x0 0x10000>,
493 + <0x0 0x1ee2140 0x0 0x4>;
494 + reg-names = "ftm", "FlexTimer1";
495 + interrupts = <0 86 0x4>;
496 + big-endian;
497 + status = "okay";
498 + };
499 +
500 wdog0: wdog@2ad0000 {
501 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
502 reg = <0x0 0x2ad0000 0x0 0x10000>;
503 @@ -611,7 +688,10 @@
504 dr_mode = "host";
505 snps,quirk-frame-length-adjustment = <0x20>;
506 snps,dis_rxdet_inp3_quirk;
507 + usb3-lpm-capable;
508 + snps,dis-u1u2-when-u3-quirk;
509 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
510 + configure-gfladj;
511 };
512
513 usb1: usb3@3000000 {
514 @@ -621,7 +701,10 @@
515 dr_mode = "host";
516 snps,quirk-frame-length-adjustment = <0x20>;
517 snps,dis_rxdet_inp3_quirk;
518 + usb3-lpm-capable;
519 + snps,dis-u1u2-when-u3-quirk;
520 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
521 + configure-gfladj;
522 };
523
524 usb2: usb3@3100000 {
525 @@ -631,7 +714,10 @@
526 dr_mode = "host";
527 snps,quirk-frame-length-adjustment = <0x20>;
528 snps,dis_rxdet_inp3_quirk;
529 + usb3-lpm-capable;
530 + snps,dis-u1u2-when-u3-quirk;
531 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
532 + configure-gfladj;
533 };
534
535 sata: sata@3200000 {
536 @@ -670,9 +756,9 @@
537 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
538 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
539 reg-names = "regs", "config";
540 - interrupts = <0 118 0x4>, /* controller interrupt */
541 - <0 117 0x4>; /* PME interrupt */
542 - interrupt-names = "intr", "pme";
543 + interrupts = <0 117 0x4>, /* PME interrupt */
544 + <0 118 0x4>; /* aer interrupt */
545 + interrupt-names = "pme", "aer";
546 #address-cells = <3>;
547 #size-cells = <2>;
548 device_type = "pci";
549 @@ -696,9 +782,9 @@
550 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
551 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
552 reg-names = "regs", "config";
553 - interrupts = <0 128 0x4>,
554 - <0 127 0x4>;
555 - interrupt-names = "intr", "pme";
556 + interrupts = <0 127 0x4>,
557 + <0 128 0x4>;
558 + interrupt-names = "pme", "aer";
559 #address-cells = <3>;
560 #size-cells = <2>;
561 device_type = "pci";
562 @@ -722,9 +808,9 @@
563 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
564 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
565 reg-names = "regs", "config";
566 - interrupts = <0 162 0x4>,
567 - <0 161 0x4>;
568 - interrupt-names = "intr", "pme";
569 + interrupts = <0 161 0x4>,
570 + <0 162 0x4>;
571 + interrupt-names = "pme", "aer";
572 #address-cells = <3>;
573 #size-cells = <2>;
574 device_type = "pci";
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