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1 From 68b6fec37f4c6fa382da4b76039743c4de89b028 Mon Sep 17 00:00:00 2001
2 From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
3 Date: Tue, 25 Jun 2019 09:09:35 +0000
4 Subject: [PATCH] PCI: mobiveil: Add PCIe Gen4 RC driver for NXP Layerscape
5 SoCs
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 This PCIe controller is based on the Mobiveil GPEX IP, which is
11 compatible with the PCI Express™ Base Specification, Revision 4.0.
12
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
15 ---
16 drivers/pci/controller/mobiveil/Kconfig | 10 +
17 drivers/pci/controller/mobiveil/Makefile | 1 +
18 .../pci/controller/mobiveil/pcie-layerscape-gen4.c | 274 +++++++++++++++++++++
19 drivers/pci/controller/mobiveil/pcie-mobiveil.h | 16 +-
20 4 files changed, 299 insertions(+), 2 deletions(-)
21 create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
22
23 --- a/drivers/pci/controller/mobiveil/Kconfig
24 +++ b/drivers/pci/controller/mobiveil/Kconfig
25 @@ -21,4 +21,14 @@ config PCIE_MOBIVEIL_PLAT
26 Soft IP. It has up to 8 outbound and inbound windows
27 for address translation and it is a PCIe Gen4 IP.
28
29 +config PCIE_LAYERSCAPE_GEN4
30 + bool "Freescale Layerscape PCIe Gen4 controller"
31 + depends on PCI
32 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
33 + depends on PCI_MSI_IRQ_DOMAIN
34 + select PCIE_MOBIVEIL_HOST
35 + help
36 + Say Y here if you want PCIe Gen4 controller support on
37 + Layerscape SoCs. The PCIe controller can work in RC or
38 + EP mode according to RCW[HOST_AGT_PEX] setting.
39 endmenu
40 --- a/drivers/pci/controller/mobiveil/Makefile
41 +++ b/drivers/pci/controller/mobiveil/Makefile
42 @@ -2,3 +2,4 @@
43 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
44 obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
45 obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
46 +obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
47 --- /dev/null
48 +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
49 @@ -0,0 +1,274 @@
50 +// SPDX-License-Identifier: GPL-2.0
51 +/*
52 + * PCIe Gen4 host controller driver for NXP Layerscape SoCs
53 + *
54 + * Copyright 2019 NXP
55 + *
56 + * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
57 + */
58 +
59 +#include <linux/kernel.h>
60 +#include <linux/interrupt.h>
61 +#include <linux/init.h>
62 +#include <linux/of_pci.h>
63 +#include <linux/of_platform.h>
64 +#include <linux/of_irq.h>
65 +#include <linux/of_address.h>
66 +#include <linux/pci.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/resource.h>
69 +#include <linux/mfd/syscon.h>
70 +#include <linux/regmap.h>
71 +
72 +#include "pcie-mobiveil.h"
73 +
74 +/* LUT and PF control registers */
75 +#define PCIE_LUT_OFF 0x80000
76 +#define PCIE_PF_OFF 0xc0000
77 +#define PCIE_PF_INT_STAT 0x18
78 +#define PF_INT_STAT_PABRST BIT(31)
79 +
80 +#define PCIE_PF_DBG 0x7fc
81 +#define PF_DBG_LTSSM_MASK 0x3f
82 +#define PF_DBG_LTSSM_L0 0x2d /* L0 state */
83 +#define PF_DBG_WE BIT(31)
84 +#define PF_DBG_PABR BIT(27)
85 +
86 +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
87 +
88 +struct ls_pcie_g4 {
89 + struct mobiveil_pcie pci;
90 + struct delayed_work dwork;
91 + int irq;
92 +};
93 +
94 +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
95 +{
96 + return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
97 +}
98 +
99 +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
100 + u32 off, u32 val)
101 +{
102 + iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
103 +}
104 +
105 +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
106 +{
107 + return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
108 +}
109 +
110 +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
111 + u32 off, u32 val)
112 +{
113 + iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
114 +}
115 +
116 +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
117 +{
118 + struct mobiveil_pcie *mv_pci = &pcie->pci;
119 + u32 header_type;
120 +
121 + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
122 + header_type &= 0x7f;
123 +
124 + return header_type == PCI_HEADER_TYPE_BRIDGE;
125 +}
126 +
127 +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
128 +{
129 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
130 + u32 state;
131 +
132 + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
133 + state = state & PF_DBG_LTSSM_MASK;
134 +
135 + if (state == PF_DBG_LTSSM_L0)
136 + return 1;
137 +
138 + return 0;
139 +}
140 +
141 +static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie)
142 +{
143 + struct mobiveil_pcie *mv_pci = &pcie->pci;
144 +
145 + csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB);
146 +}
147 +
148 +static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie)
149 +{
150 + struct mobiveil_pcie *mv_pci = &pcie->pci;
151 + u32 val;
152 +
153 + /* Clear the interrupt status */
154 + csr_writel(mv_pci, 0xffffffff, PAB_INTP_AMBA_MISC_STAT);
155 +
156 + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
157 + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
158 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
159 +}
160 +
161 +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
162 +{
163 + struct mobiveil_pcie *mv_pci = &pcie->pci;
164 + struct device *dev = &mv_pci->pdev->dev;
165 + u32 val, act_stat;
166 + int to = 100;
167 +
168 + /* Poll for pab_csb_reset to set and PAB activity to clear */
169 + do {
170 + usleep_range(10, 15);
171 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
172 + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
173 + } while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
174 + if (to < 0) {
175 + dev_err(dev, "Poll PABRST&PABACT timeout\n");
176 + return;
177 + }
178 +
179 + /* clear PEX_RESET bit in PEX_PF0_DBG register */
180 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
181 + val |= PF_DBG_WE;
182 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
183 +
184 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
185 + val |= PF_DBG_PABR;
186 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
187 +
188 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
189 + val &= ~PF_DBG_WE;
190 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
191 +
192 + mobiveil_host_init(mv_pci, true);
193 +
194 + to = 100;
195 + while (!ls_pcie_g4_link_up(mv_pci) && to--)
196 + usleep_range(200, 250);
197 + if (to < 0)
198 + dev_err(dev, "PCIe link training timeout\n");
199 +}
200 +
201 +static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id)
202 +{
203 + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;
204 + struct mobiveil_pcie *mv_pci = &pcie->pci;
205 + u32 val;
206 +
207 + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT);
208 + if (!val)
209 + return IRQ_NONE;
210 +
211 + if (val & PAB_INTP_RESET) {
212 + ls_pcie_g4_disable_interrupt(pcie);
213 + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));
214 + }
215 +
216 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT);
217 +
218 + return IRQ_HANDLED;
219 +}
220 +
221 +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci)
222 +{
223 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);
224 + struct platform_device *pdev = mv_pci->pdev;
225 + struct device *dev = &pdev->dev;
226 + int ret;
227 +
228 + pcie->irq = platform_get_irq_byname(pdev, "intr");
229 + if (pcie->irq < 0) {
230 + dev_err(dev, "Can't get 'intr' IRQ, errno = %d\n", pcie->irq);
231 + return pcie->irq;
232 + }
233 + ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr,
234 + IRQF_SHARED, pdev->name, pcie);
235 + if (ret) {
236 + dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret);
237 + return ret;
238 + }
239 +
240 + return 0;
241 +}
242 +
243 +static void ls_pcie_g4_reset(struct work_struct *work)
244 +{
245 + struct delayed_work *dwork = container_of(work, struct delayed_work,
246 + work);
247 + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);
248 + struct mobiveil_pcie *mv_pci = &pcie->pci;
249 + u16 ctrl;
250 +
251 + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL);
252 + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
253 + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
254 + ls_pcie_g4_reinit_hw(pcie);
255 + ls_pcie_g4_enable_interrupt(pcie);
256 +}
257 +
258 +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
259 + .interrupt_init = ls_pcie_g4_interrupt_init,
260 +};
261 +
262 +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
263 + .link_up = ls_pcie_g4_link_up,
264 +};
265 +
266 +static int __init ls_pcie_g4_probe(struct platform_device *pdev)
267 +{
268 + struct device *dev = &pdev->dev;
269 + struct pci_host_bridge *bridge;
270 + struct mobiveil_pcie *mv_pci;
271 + struct ls_pcie_g4 *pcie;
272 + struct device_node *np = dev->of_node;
273 + int ret;
274 +
275 + if (!of_parse_phandle(np, "msi-parent", 0)) {
276 + dev_err(dev, "Failed to find msi-parent\n");
277 + return -EINVAL;
278 + }
279 +
280 + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
281 + if (!bridge)
282 + return -ENOMEM;
283 +
284 + pcie = pci_host_bridge_priv(bridge);
285 + mv_pci = &pcie->pci;
286 +
287 + mv_pci->pdev = pdev;
288 + mv_pci->ops = &ls_pcie_g4_pab_ops;
289 + mv_pci->rp.ops = &ls_pcie_g4_rp_ops;
290 + mv_pci->bridge = bridge;
291 +
292 + platform_set_drvdata(pdev, pcie);
293 +
294 + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset);
295 +
296 + ret = mobiveil_pcie_host_probe(mv_pci);
297 + if (ret) {
298 + dev_err(dev, "Fail to probe\n");
299 + return ret;
300 + }
301 +
302 + if (!ls_pcie_g4_is_bridge(pcie))
303 + return -ENODEV;
304 +
305 + ls_pcie_g4_enable_interrupt(pcie);
306 +
307 + return 0;
308 +}
309 +
310 +static const struct of_device_id ls_pcie_g4_of_match[] = {
311 + { .compatible = "fsl,lx2160a-pcie", },
312 + { },
313 +};
314 +
315 +static struct platform_driver ls_pcie_g4_driver = {
316 + .driver = {
317 + .name = "layerscape-pcie-gen4",
318 + .of_match_table = ls_pcie_g4_of_match,
319 + .suppress_bind_attrs = true,
320 + },
321 +};
322 +
323 +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
324 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
325 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
326 @@ -43,6 +43,8 @@
327 #define PAGE_LO_MASK 0x3ff
328 #define PAGE_SEL_OFFSET_SHIFT 10
329
330 +#define PAB_ACTIVITY_STAT 0x81c
331 +
332 #define PAB_AXI_PIO_CTRL 0x0840
333 #define APIO_EN_MASK 0xf
334
335 @@ -51,8 +53,18 @@
336
337 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
338 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
339 -#define PAB_INTP_INTX_MASK 0x01e0
340 -#define PAB_INTP_MSI_MASK 0x8
341 +#define PAB_INTP_RESET BIT(1)
342 +#define PAB_INTP_MSI BIT(3)
343 +#define PAB_INTP_INTA BIT(5)
344 +#define PAB_INTP_INTB BIT(6)
345 +#define PAB_INTP_INTC BIT(7)
346 +#define PAB_INTP_INTD BIT(8)
347 +#define PAB_INTP_PCIE_UE BIT(9)
348 +#define PAB_INTP_IE_PMREDI BIT(29)
349 +#define PAB_INTP_IE_EC BIT(30)
350 +#define PAB_INTP_MSI_MASK PAB_INTP_MSI
351 +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
352 + PAB_INTP_INTC | PAB_INTP_INTD)
353
354 #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
355 #define WIN_ENABLE_SHIFT 0
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