git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Sat, 23 Apr 2016 12:34:59 +0530
   4 Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS
   5  attribute
   6
   7 When switching between the early and final mmu tables, the stack will
   8 get corrupted if the Non-Secure attribute is different.  For ls1043a,
   9 this issue is currently masked because flush_dcache_all is called
  10 before the switch when CONFIG_SYS_DPAA_FMAN is defined.
  11
  12 Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
  13 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  14 ---
  15  arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   12 ++++++++----
  16  1 file changed, 8 insertions(+), 4 deletions(-)
  17
  18 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
  19 index a9dadfa..a7522da 100644
  20 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
  21 +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
  22 @@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
  23         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  24           CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  25         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  26 -         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  27 +         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  28 +         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
  29         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  30 -         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  31 +         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
  32 +         PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
  33  #endif
  34  };
  35
  36 @@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
  37           CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
  38           PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
  39         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  40 -         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  41 +         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
  42 +         PMD_SECT_OUTER_SHARE | PMD_SECT_NS},
  43         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
  44           CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
  45           PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
  46 @@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
  47           CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
  48           PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
  49         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  50 -         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  51 +         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
  52 +         PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
  53  #endif
  54  };
  55  #endif
  56 --
  57 1.7.9.5
  58