git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001
   2 From: Aleksander Jan Bajkowski <olek2@wp.pl>
   3 Date: Tue, 14 Sep 2021 23:21:01 +0200
   4 Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by
   5  the drivers
   6
   7 Make the burst length configurable by the drivers.
   8
   9 Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
  10 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
  11 Signed-off-by: David S. Miller <davem@davemloft.net>
  12 ---
  13  .../include/asm/mach-lantiq/xway/xway_dma.h   |  2 +-
  14  arch/mips/lantiq/xway/dma.c                   | 38 ++++++++++++++++---
  15  2 files changed, 34 insertions(+), 6 deletions(-)
  16
  17 --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
  18 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
  19 @@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma
  20  extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
  21  extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
  22  extern void ltq_dma_free(struct ltq_dma_channel *ch);
  23 -extern void ltq_dma_init_port(int p);
  24 +extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
  25
  26  #endif
  27 --- a/arch/mips/lantiq/xway/dma.c
  28 +++ b/arch/mips/lantiq/xway/dma.c
  29 @@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)
  30  EXPORT_SYMBOL_GPL(ltq_dma_free);
  31
  32  void
  33 -ltq_dma_init_port(int p)
  34 +ltq_dma_init_port(int p, int tx_burst, int rx_burst)
  35  {
  36         ltq_dma_w32(p, LTQ_DMA_PS);
  37         switch (p) {
  38 @@ -190,16 +190,44 @@ ltq_dma_init_port(int p)
  39                  * Tell the DMA engine to swap the endianness of data frames and
  40                  * drop packets if the channel arbitration fails.
  41                  */
  42 -               ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
  43 +               ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
  44                         LTQ_DMA_PCTRL);
  45                 break;
  46
  47 -       case DMA_PORT_DEU:
  48 -               ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
  49 -                       (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
  50 +       default:
  51 +               break;
  52 +       }
  53 +
  54 +       switch (rx_burst) {
  55 +       case 8:
  56 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
  57                         LTQ_DMA_PCTRL);
  58                 break;
  59 +       case 4:
  60 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
  61 +                       LTQ_DMA_PCTRL);
  62 +               break;
  63 +       case 2:
  64 +               ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
  65 +                       LTQ_DMA_PCTRL);
  66 +               break;
  67 +       default:
  68 +               break;
  69 +       }
  70
  71 +       switch (tx_burst) {
  72 +       case 8:
  73 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
  74 +                       LTQ_DMA_PCTRL);
  75 +               break;
  76 +       case 4:
  77 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
  78 +                       LTQ_DMA_PCTRL);
  79 +               break;
  80 +       case 2:
  81 +               ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
  82 +                       LTQ_DMA_PCTRL);
  83 +               break;
  84         default:
  85                 break;
  86         }