projects / openwrt / staging / blogic.git / blob
? search:


3385edd39ddf7948c5b790a76a8681f467aa7304
[openwrt/staging/blogic.git] /
1 From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Sun, 11 Jun 2023 00:48:10 +0100
4 Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
5
6 Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
7 PHYs which require calibration data from the SoC's efuse.
8 Despite the similar design the driver doesn't share any code with the
9 existing mediatek-ge.c.
10 Add support for such PHYs by introducing a new driver with basic
11 support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
12
13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
15 Signed-off-by: David S. Miller <davem@davemloft.net>
16 ---
17 MAINTAINERS | 9 +
18 drivers/net/phy/Kconfig | 12 +
19 drivers/net/phy/Makefile | 1 +
20 drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
21 drivers/net/phy/mediatek-ge.c | 3 +-
22 5 files changed, 1140 insertions(+), 1 deletion(-)
23 create mode 100644 drivers/net/phy/mediatek-ge-soc.c
24
25 --- a/MAINTAINERS
26 +++ b/MAINTAINERS
27 @@ -12938,6 +12938,15 @@ F: drivers/net/pcs/pcs-mtk-usxgmii.c
28 F: include/linux/pcs/pcs-mtk-lynxi.h
29 F: include/linux/pcs/pcs-mtk-usxgmii.h
30
31 +MEDIATEK ETHERNET PHY DRIVERS
32 +M: Daniel Golle <daniel@makrotopia.org>
33 +M: Qingfang Deng <dqfext@gmail.com>
34 +M: SkyLake Huang <SkyLake.Huang@mediatek.com>
35 +L: netdev@vger.kernel.org
36 +S: Maintained
37 +F: drivers/net/phy/mediatek-ge-soc.c
38 +F: drivers/net/phy/mediatek-ge.c
39 +
40 MEDIATEK I2C CONTROLLER DRIVER
41 M: Qii Wang <qii.wang@mediatek.com>
42 L: linux-i2c@vger.kernel.org
43 --- a/drivers/net/phy/Kconfig
44 +++ b/drivers/net/phy/Kconfig
45 @@ -309,6 +309,18 @@ config MEDIATEK_GE_PHY
46 help
47 Supports the MediaTek Gigabit Ethernet PHYs.
48
49 +config MEDIATEK_GE_SOC_PHY
50 + tristate "MediaTek SoC Ethernet PHYs"
51 + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
52 + select NVMEM_MTK_EFUSE
53 + help
54 + Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
55 +
56 + Include support for built-in Ethernet PHYs which are present in
57 + the MT7981 and MT7988 SoCs. These PHYs need calibration data
58 + present in the SoCs efuse and will dynamically calibrate VCM
59 + (common-mode voltage) during startup.
60 +
61 config MICREL_PHY
62 tristate "Micrel PHYs"
63 depends on PTP_1588_CLOCK_OPTIONAL
64 --- a/drivers/net/phy/Makefile
65 +++ b/drivers/net/phy/Makefile
66 @@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
67 obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
68 obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
69 obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
70 +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
71 obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
72 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
73 obj-$(CONFIG_MICREL_PHY) += micrel.o
74 --- /dev/null
75 +++ b/drivers/net/phy/mediatek-ge-soc.c
76 @@ -0,0 +1,1116 @@
77 +// SPDX-License-Identifier: GPL-2.0+
78 +#include <linux/bitfield.h>
79 +#include <linux/module.h>
80 +#include <linux/nvmem-consumer.h>
81 +#include <linux/of_address.h>
82 +#include <linux/of_platform.h>
83 +#include <linux/pinctrl/consumer.h>
84 +#include <linux/phy.h>
85 +
86 +#define MTK_GPHY_ID_MT7981 0x03a29461
87 +#define MTK_GPHY_ID_MT7988 0x03a29481
88 +
89 +#define MTK_EXT_PAGE_ACCESS 0x1f
90 +#define MTK_PHY_PAGE_STANDARD 0x0000
91 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
92 +
93 +#define MTK_PHY_LPI_REG_14 0x14
94 +#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
95 +
96 +#define MTK_PHY_LPI_REG_1c 0x1c
97 +#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
98 +
99 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
100 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
101 +
102 +#define ANALOG_INTERNAL_OPERATION_MAX_US 20
103 +#define TXRESERVE_MIN 0
104 +#define TXRESERVE_MAX 7
105 +
106 +#define MTK_PHY_ANARG_RG 0x10
107 +#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
108 +
109 +/* Registers on MDIO_MMD_VEND1 */
110 +#define MTK_PHY_TXVLD_DA_RG 0x12
111 +#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
112 +#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
113 +
114 +#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
115 +#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
116 +#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
117 +
118 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
119 +#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
120 +#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
121 +
122 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
123 +#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
124 +#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
125 +
126 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
127 +#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
128 +#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
129 +
130 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
131 +#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
132 +#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
133 +
134 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
135 +#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
136 +#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
137 +
138 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
139 +#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
140 +#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
141 +
142 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
143 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
144 +
145 +#define MTK_PHY_RXADC_CTRL_RG9 0xc8
146 +#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
147 +#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
148 +#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
149 +#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
150 +
151 +#define MTK_PHY_LDO_OUTPUT_V 0xd7
152 +
153 +#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
154 +#define MTK_PHY_RG_CAL_CKINV BIT(12)
155 +#define MTK_PHY_RG_ANA_CALEN BIT(8)
156 +#define MTK_PHY_RG_ZCALEN_A BIT(0)
157 +
158 +#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
159 +#define MTK_PHY_RG_ZCALEN_B BIT(12)
160 +#define MTK_PHY_RG_ZCALEN_C BIT(8)
161 +#define MTK_PHY_RG_ZCALEN_D BIT(4)
162 +#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
163 +
164 +#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
165 +#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
166 +
167 +#define MTK_PHY_RG_TX_FILTER 0xfe
168 +
169 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
170 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
171 +#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
172 +
173 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
174 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
175 +
176 +#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
177 +#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
178 +
179 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
180 +#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
181 +#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
182 +
183 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
184 +#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
185 +#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
186 +
187 +#define MTK_PHY_RG_AD_CAL_COMP 0x17a
188 +#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
189 +
190 +#define MTK_PHY_RG_AD_CAL_CLK 0x17b
191 +#define MTK_PHY_DA_CAL_CLK BIT(0)
192 +
193 +#define MTK_PHY_RG_AD_CALIN 0x17c
194 +#define MTK_PHY_DA_CALIN_FLAG BIT(0)
195 +
196 +#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
197 +#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
198 +
199 +#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
200 +#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
201 +
202 +#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
203 +#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
204 +
205 +#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
206 +#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
207 +
208 +#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
209 +#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
210 +
211 +#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
212 +#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
213 +
214 +#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
215 +#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
216 +
217 +#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
218 +#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
219 +
220 +#define MTK_PHY_RG_DEV1E_REG19b 0x19b
221 +#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
222 +
223 +#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
224 +#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
225 +#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
226 +#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
227 +#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
228 +#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
229 +#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
230 +#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
231 +#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
232 +#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
233 +
234 +#define MTK_PHY_RG_DEV1E_REG234 0x234
235 +#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
236 +#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
237 +#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
238 +
239 +#define MTK_PHY_RG_LPF_CNT_VAL 0x235
240 +
241 +#define MTK_PHY_RG_DEV1E_REG238 0x238
242 +#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
243 +#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
244 +
245 +#define MTK_PHY_RG_DEV1E_REG239 0x239
246 +#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
247 +#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
248 +
249 +#define MTK_PHY_RG_DEV1E_REG27C 0x27c
250 +#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
251 +#define MTK_PHY_RG_DEV1E_REG27D 0x27d
252 +#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
253 +
254 +#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
255 +#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
256 +#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
257 +
258 +#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
259 +#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
260 +#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
261 +#define MTK_PHY_LPI_TR_READY BIT(9)
262 +#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
263 +
264 +#define MTK_PHY_RG_DEV1E_REG323 0x323
265 +#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
266 +#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
267 +
268 +#define MTK_PHY_RG_DEV1E_REG324 0x324
269 +#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
270 +#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
271 +
272 +#define MTK_PHY_RG_DEV1E_REG326 0x326
273 +#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
274 +#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
275 +#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
276 +#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
277 +#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
278 +
279 +#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
280 +#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
281 +
282 +#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
283 +#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
284 +#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
285 +#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
286 +
287 +#define MTK_PHY_RG_BG_RASEL 0x115
288 +#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
289 +
290 +/* These macro privides efuse parsing for internal phy. */
291 +#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
292 +#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
293 +#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
294 +#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
295 +#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
296 +
297 +#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
298 +#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
299 +#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
300 +#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
301 +#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
302 +
303 +#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
304 +#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
305 +
306 +#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
307 +#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
308 +
309 +enum {
310 + NO_PAIR,
311 + PAIR_A,
312 + PAIR_B,
313 + PAIR_C,
314 + PAIR_D,
315 +};
316 +
317 +enum {
318 + GPHY_PORT0,
319 + GPHY_PORT1,
320 + GPHY_PORT2,
321 + GPHY_PORT3,
322 +};
323 +
324 +enum calibration_mode {
325 + EFUSE_K,
326 + SW_K
327 +};
328 +
329 +enum CAL_ITEM {
330 + REXT,
331 + TX_OFFSET,
332 + TX_AMP,
333 + TX_R50,
334 + TX_VCM
335 +};
336 +
337 +enum CAL_MODE {
338 + EFUSE_M,
339 + SW_M
340 +};
341 +
342 +static int mtk_socphy_read_page(struct phy_device *phydev)
343 +{
344 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
345 +}
346 +
347 +static int mtk_socphy_write_page(struct phy_device *phydev, int page)
348 +{
349 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
350 +}
351 +
352 +/* One calibration cycle consists of:
353 + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
354 + * until AD_CAL_COMP is ready to output calibration result.
355 + * 2.Wait until DA_CAL_CLK is available.
356 + * 3.Fetch AD_CAL_COMP_OUT.
357 + */
358 +static int cal_cycle(struct phy_device *phydev, int devad,
359 + u32 regnum, u16 mask, u16 cal_val)
360 +{
361 + int reg_val;
362 + int ret;
363 +
364 + phy_modify_mmd(phydev, devad, regnum,
365 + mask, cal_val);
366 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
367 + MTK_PHY_DA_CALIN_FLAG);
368 +
369 + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
370 + MTK_PHY_RG_AD_CAL_CLK, reg_val,
371 + reg_val & MTK_PHY_DA_CAL_CLK, 500,
372 + ANALOG_INTERNAL_OPERATION_MAX_US, false);
373 + if (ret) {
374 + phydev_err(phydev, "Calibration cycle timeout\n");
375 + return ret;
376 + }
377 +
378 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
379 + MTK_PHY_DA_CALIN_FLAG);
380 + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
381 + MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
382 + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
383 +
384 + return ret;
385 +}
386 +
387 +static int rext_fill_result(struct phy_device *phydev, u16 *buf)
388 +{
389 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
390 + MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
391 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
392 + MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
393 +
394 + return 0;
395 +}
396 +
397 +static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
398 +{
399 + u16 rext_cal_val[2];
400 +
401 + rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
402 + rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
403 + rext_fill_result(phydev, rext_cal_val);
404 +
405 + return 0;
406 +}
407 +
408 +static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
409 +{
410 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
411 + MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
412 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
413 + MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
414 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
415 + MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
416 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
417 + MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
418 +
419 + return 0;
420 +}
421 +
422 +static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
423 +{
424 + u16 tx_offset_cal_val[4];
425 +
426 + tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
427 + tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
428 + tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
429 + tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
430 +
431 + tx_offset_fill_result(phydev, tx_offset_cal_val);
432 +
433 + return 0;
434 +}
435 +
436 +static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
437 +{
438 + int i;
439 + int bias[16] = {};
440 + const int vals_9461[16] = { 7, 1, 4, 7,
441 + 7, 1, 4, 7,
442 + 7, 1, 4, 7,
443 + 7, 1, 4, 7 };
444 + const int vals_9481[16] = { 10, 6, 6, 10,
445 + 10, 6, 6, 10,
446 + 10, 6, 6, 10,
447 + 10, 6, 6, 10 };
448 + switch (phydev->drv->phy_id) {
449 + case MTK_GPHY_ID_MT7981:
450 + /* We add some calibration to efuse values
451 + * due to board level influence.
452 + * GBE: +7, TBT: +1, HBT: +4, TST: +7
453 + */
454 + memcpy(bias, (const void *)vals_9461, sizeof(bias));
455 + break;
456 + case MTK_GPHY_ID_MT7988:
457 + memcpy(bias, (const void *)vals_9481, sizeof(bias));
458 + break;
459 + }
460 +
461 + /* Prevent overflow */
462 + for (i = 0; i < 12; i++) {
463 + if (buf[i >> 2] + bias[i] > 63) {
464 + buf[i >> 2] = 63;
465 + bias[i] = 0;
466 + }
467 + }
468 +
469 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
470 + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
471 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
472 + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
473 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
474 + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
475 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
476 + MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
477 +
478 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
479 + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
480 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
481 + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
482 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
483 + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
484 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
485 + MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
486 +
487 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
488 + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
489 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
490 + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
491 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
492 + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
493 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
494 + MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
495 +
496 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
497 + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
498 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
499 + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
500 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
501 + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
502 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
503 + MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
504 +
505 + return 0;
506 +}
507 +
508 +static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
509 +{
510 + u16 tx_amp_cal_val[4];
511 +
512 + tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
513 + tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
514 + tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
515 + tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
516 + tx_amp_fill_result(phydev, tx_amp_cal_val);
517 +
518 + return 0;
519 +}
520 +
521 +static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
522 + u8 txg_calen_x)
523 +{
524 + int bias = 0;
525 + u16 reg, val;
526 +
527 + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
528 + bias = -2;
529 +
530 + val = clamp_val(bias + tx_r50_cal_val, 0, 63);
531 +
532 + switch (txg_calen_x) {
533 + case PAIR_A:
534 + reg = MTK_PHY_DA_TX_R50_PAIR_A;
535 + break;
536 + case PAIR_B:
537 + reg = MTK_PHY_DA_TX_R50_PAIR_B;
538 + break;
539 + case PAIR_C:
540 + reg = MTK_PHY_DA_TX_R50_PAIR_C;
541 + break;
542 + case PAIR_D:
543 + reg = MTK_PHY_DA_TX_R50_PAIR_D;
544 + break;
545 + default:
546 + return -EINVAL;
547 + }
548 +
549 + phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
550 +
551 + return 0;
552 +}
553 +
554 +static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
555 + u8 txg_calen_x)
556 +{
557 + u16 tx_r50_cal_val;
558 +
559 + switch (txg_calen_x) {
560 + case PAIR_A:
561 + tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
562 + break;
563 + case PAIR_B:
564 + tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
565 + break;
566 + case PAIR_C:
567 + tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
568 + break;
569 + case PAIR_D:
570 + tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
571 + break;
572 + default:
573 + return -EINVAL;
574 + }
575 + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
576 +
577 + return 0;
578 +}
579 +
580 +static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
581 +{
582 + u8 lower_idx, upper_idx, txreserve_val;
583 + u8 lower_ret, upper_ret;
584 + int ret;
585 +
586 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
587 + MTK_PHY_RG_ANA_CALEN);
588 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
589 + MTK_PHY_RG_CAL_CKINV);
590 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
591 + MTK_PHY_RG_TXVOS_CALEN);
592 +
593 + switch (rg_txreserve_x) {
594 + case PAIR_A:
595 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
596 + MTK_PHY_RG_DASN_DAC_IN0_A,
597 + MTK_PHY_DASN_DAC_IN0_A_MASK);
598 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
599 + MTK_PHY_RG_DASN_DAC_IN1_A,
600 + MTK_PHY_DASN_DAC_IN1_A_MASK);
601 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
602 + MTK_PHY_RG_ANA_CAL_RG0,
603 + MTK_PHY_RG_ZCALEN_A);
604 + break;
605 + case PAIR_B:
606 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
607 + MTK_PHY_RG_DASN_DAC_IN0_B,
608 + MTK_PHY_DASN_DAC_IN0_B_MASK);
609 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
610 + MTK_PHY_RG_DASN_DAC_IN1_B,
611 + MTK_PHY_DASN_DAC_IN1_B_MASK);
612 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
613 + MTK_PHY_RG_ANA_CAL_RG1,
614 + MTK_PHY_RG_ZCALEN_B);
615 + break;
616 + case PAIR_C:
617 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
618 + MTK_PHY_RG_DASN_DAC_IN0_C,
619 + MTK_PHY_DASN_DAC_IN0_C_MASK);
620 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
621 + MTK_PHY_RG_DASN_DAC_IN1_C,
622 + MTK_PHY_DASN_DAC_IN1_C_MASK);
623 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
624 + MTK_PHY_RG_ANA_CAL_RG1,
625 + MTK_PHY_RG_ZCALEN_C);
626 + break;
627 + case PAIR_D:
628 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
629 + MTK_PHY_RG_DASN_DAC_IN0_D,
630 + MTK_PHY_DASN_DAC_IN0_D_MASK);
631 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
632 + MTK_PHY_RG_DASN_DAC_IN1_D,
633 + MTK_PHY_DASN_DAC_IN1_D_MASK);
634 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
635 + MTK_PHY_RG_ANA_CAL_RG1,
636 + MTK_PHY_RG_ZCALEN_D);
637 + break;
638 + default:
639 + ret = -EINVAL;
640 + goto restore;
641 + }
642 +
643 + lower_idx = TXRESERVE_MIN;
644 + upper_idx = TXRESERVE_MAX;
645 +
646 + phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
647 + while ((upper_idx - lower_idx) > 1) {
648 + txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
649 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
650 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
651 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
652 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
653 + MTK_PHY_DA_RX_PSBN_LP_MASK,
654 + txreserve_val << 12 | txreserve_val << 8 |
655 + txreserve_val << 4 | txreserve_val);
656 + if (ret == 1) {
657 + upper_idx = txreserve_val;
658 + upper_ret = ret;
659 + } else if (ret == 0) {
660 + lower_idx = txreserve_val;
661 + lower_ret = ret;
662 + } else {
663 + goto restore;
664 + }
665 + }
666 +
667 + if (lower_idx == TXRESERVE_MIN) {
668 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
669 + MTK_PHY_RXADC_CTRL_RG9,
670 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
671 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
672 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
673 + MTK_PHY_DA_RX_PSBN_LP_MASK,
674 + lower_idx << 12 | lower_idx << 8 |
675 + lower_idx << 4 | lower_idx);
676 + ret = lower_ret;
677 + } else if (upper_idx == TXRESERVE_MAX) {
678 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
679 + MTK_PHY_RXADC_CTRL_RG9,
680 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
681 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
682 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
683 + MTK_PHY_DA_RX_PSBN_LP_MASK,
684 + upper_idx << 12 | upper_idx << 8 |
685 + upper_idx << 4 | upper_idx);
686 + ret = upper_ret;
687 + }
688 + if (ret < 0)
689 + goto restore;
690 +
691 + /* We calibrate TX-VCM in different logic. Check upper index and then
692 + * lower index. If this calibration is valid, apply lower index's result.
693 + */
694 + ret = upper_ret - lower_ret;
695 + if (ret == 1) {
696 + ret = 0;
697 + /* Make sure we use upper_idx in our calibration system */
698 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
699 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
700 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
701 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
702 + MTK_PHY_DA_RX_PSBN_LP_MASK,
703 + upper_idx << 12 | upper_idx << 8 |
704 + upper_idx << 4 | upper_idx);
705 + phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
706 + } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
707 + lower_ret == 1) {
708 + ret = 0;
709 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
710 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
711 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
712 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
713 + MTK_PHY_DA_RX_PSBN_LP_MASK,
714 + lower_idx << 12 | lower_idx << 8 |
715 + lower_idx << 4 | lower_idx);
716 + phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
717 + lower_idx);
718 + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
719 + lower_ret == 0) {
720 + ret = 0;
721 + phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
722 + upper_idx);
723 + } else {
724 + ret = -EINVAL;
725 + }
726 +
727 +restore:
728 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
729 + MTK_PHY_RG_ANA_CALEN);
730 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
731 + MTK_PHY_RG_TXVOS_CALEN);
732 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
733 + MTK_PHY_RG_ZCALEN_A);
734 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
735 + MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
736 + MTK_PHY_RG_ZCALEN_D);
737 +
738 + return ret;
739 +}
740 +
741 +static void mt798x_phy_common_finetune(struct phy_device *phydev)
742 +{
743 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
744 + /* EnabRandUpdTrig = 1 */
745 + __phy_write(phydev, 0x11, 0x2f00);
746 + __phy_write(phydev, 0x12, 0xe);
747 + __phy_write(phydev, 0x10, 0x8fb0);
748 +
749 + /* NormMseLoThresh = 85 */
750 + __phy_write(phydev, 0x11, 0x55a0);
751 + __phy_write(phydev, 0x12, 0x0);
752 + __phy_write(phydev, 0x10, 0x83aa);
753 +
754 + /* TrFreeze = 0 */
755 + __phy_write(phydev, 0x11, 0x0);
756 + __phy_write(phydev, 0x12, 0x0);
757 + __phy_write(phydev, 0x10, 0x9686);
758 +
759 + /* SSTrKp1000Slv = 5 */
760 + __phy_write(phydev, 0x11, 0xbaef);
761 + __phy_write(phydev, 0x12, 0x2e);
762 + __phy_write(phydev, 0x10, 0x968c);
763 +
764 + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
765 + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
766 + */
767 + __phy_write(phydev, 0x11, 0xd10a);
768 + __phy_write(phydev, 0x12, 0x34);
769 + __phy_write(phydev, 0x10, 0x8f82);
770 +
771 + /* VcoSlicerThreshBitsHigh */
772 + __phy_write(phydev, 0x11, 0x5555);
773 + __phy_write(phydev, 0x12, 0x55);
774 + __phy_write(phydev, 0x10, 0x8ec0);
775 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
776 +
777 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
778 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
779 + MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
780 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
781 +
782 + /* rg_tr_lpf_cnt_val = 512 */
783 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
784 +
785 + /* IIR2 related */
786 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
787 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
788 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
789 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
790 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
791 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
792 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
793 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
794 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
795 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
796 +
797 + /* FFE peaking */
798 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
799 + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
800 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
801 + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
802 +
803 + /* Disable LDO pump */
804 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
805 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
806 + /* Adjust LDO output voltage */
807 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
808 +}
809 +
810 +static void mt7981_phy_finetune(struct phy_device *phydev)
811 +{
812 + u16 val[8] = { 0x01ce, 0x01c1,
813 + 0x020f, 0x0202,
814 + 0x03d0, 0x03c0,
815 + 0x0013, 0x0005 };
816 + int i, k;
817 +
818 + /* 100M eye finetune:
819 + * Keep middle level of TX MLT3 shapper as default.
820 + * Only change TX MLT3 overshoot level here.
821 + */
822 + for (k = 0, i = 1; i < 12; i++) {
823 + if (i % 3 == 0)
824 + continue;
825 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
826 + }
827 +
828 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
829 + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
830 + __phy_write(phydev, 0x11, 0xc71);
831 + __phy_write(phydev, 0x12, 0xc);
832 + __phy_write(phydev, 0x10, 0x8fae);
833 +
834 + /* ResetSyncOffset = 6 */
835 + __phy_write(phydev, 0x11, 0x600);
836 + __phy_write(phydev, 0x12, 0x0);
837 + __phy_write(phydev, 0x10, 0x8fc0);
838 +
839 + /* VgaDecRate = 1 */
840 + __phy_write(phydev, 0x11, 0x4c2a);
841 + __phy_write(phydev, 0x12, 0x3e);
842 + __phy_write(phydev, 0x10, 0x8fa4);
843 +
844 + /* FfeUpdGainForce = 4 */
845 + __phy_write(phydev, 0x11, 0x240);
846 + __phy_write(phydev, 0x12, 0x0);
847 + __phy_write(phydev, 0x10, 0x9680);
848 +
849 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
850 +}
851 +
852 +static void mt7988_phy_finetune(struct phy_device *phydev)
853 +{
854 + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
855 + 0x020d, 0x0206, 0x0384, 0x03d0,
856 + 0x03c6, 0x030a, 0x0011, 0x0005 };
857 + int i;
858 +
859 + /* Set default MLT3 shaper first */
860 + for (i = 0; i < 12; i++)
861 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
862 +
863 + /* TCT finetune */
864 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
865 +
866 + /* Disable TX power saving */
867 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
868 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
869 +
870 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
871 +
872 + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
873 + __phy_write(phydev, 0x11, 0x671);
874 + __phy_write(phydev, 0x12, 0xc);
875 + __phy_write(phydev, 0x10, 0x8fae);
876 +
877 + /* ResetSyncOffset = 5 */
878 + __phy_write(phydev, 0x11, 0x500);
879 + __phy_write(phydev, 0x12, 0x0);
880 + __phy_write(phydev, 0x10, 0x8fc0);
881 +
882 + /* VgaDecRate is 1 at default on mt7988 */
883 +
884 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
885 +
886 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
887 + /* TxClkOffset = 2 */
888 + __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
889 + FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
890 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
891 +}
892 +
893 +static void mt798x_phy_eee(struct phy_device *phydev)
894 +{
895 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
896 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
897 + MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
898 + MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
899 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
900 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
901 +
902 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
903 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
904 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
905 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
906 + 0xff));
907 +
908 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
909 + MTK_PHY_RG_TESTMUX_ADC_CTRL,
910 + MTK_PHY_RG_TXEN_DIG_MASK);
911 +
912 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
913 + MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
914 +
915 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
916 + MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
917 +
918 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
919 + MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
920 + MTK_PHY_LPI_SLV_SEND_TX_EN,
921 + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
922 +
923 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
924 + MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
925 + MTK_PHY_LPI_TXPCS_LOC_RCV,
926 + FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
927 +
928 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
929 + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
930 + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
931 + FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
932 +
933 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
934 + MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
935 + FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
936 + 0x33) |
937 + MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
938 + MTK_PHY_LPI_VCO_EEE_STG0_EN);
939 +
940 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
941 + MTK_PHY_EEE_WAKE_MAS_INT_DC |
942 + MTK_PHY_EEE_WAKE_SLV_INT_DC);
943 +
944 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
945 + MTK_PHY_SMI_DETCNT_MAX_MASK,
946 + FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
947 + MTK_PHY_SMI_DET_MAX_EN);
948 +
949 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
950 + MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
951 + MTK_PHY_TREC_UPDATE_ENAB_CLR |
952 + MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
953 + MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
954 +
955 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
956 + /* Regsigdet_sel_1000 = 0 */
957 + __phy_write(phydev, 0x11, 0xb);
958 + __phy_write(phydev, 0x12, 0x0);
959 + __phy_write(phydev, 0x10, 0x9690);
960 +
961 + /* REG_EEE_st2TrKf1000 = 3 */
962 + __phy_write(phydev, 0x11, 0x114f);
963 + __phy_write(phydev, 0x12, 0x2);
964 + __phy_write(phydev, 0x10, 0x969a);
965 +
966 + /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
967 + __phy_write(phydev, 0x11, 0x3028);
968 + __phy_write(phydev, 0x12, 0x0);
969 + __phy_write(phydev, 0x10, 0x969e);
970 +
971 + /* RegEEE_slv_wake_int_timer_tar = 8 */
972 + __phy_write(phydev, 0x11, 0x5010);
973 + __phy_write(phydev, 0x12, 0x0);
974 + __phy_write(phydev, 0x10, 0x96a0);
975 +
976 + /* RegEEE_trfreeze_timer2 = 586 */
977 + __phy_write(phydev, 0x11, 0x24a);
978 + __phy_write(phydev, 0x12, 0x0);
979 + __phy_write(phydev, 0x10, 0x96a8);
980 +
981 + /* RegEEE100Stg1_tar = 16 */
982 + __phy_write(phydev, 0x11, 0x3210);
983 + __phy_write(phydev, 0x12, 0x0);
984 + __phy_write(phydev, 0x10, 0x96b8);
985 +
986 + /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
987 + __phy_write(phydev, 0x11, 0x1463);
988 + __phy_write(phydev, 0x12, 0x0);
989 + __phy_write(phydev, 0x10, 0x96ca);
990 +
991 + /* DfeTailEnableVgaThresh1000 = 27 */
992 + __phy_write(phydev, 0x11, 0x36);
993 + __phy_write(phydev, 0x12, 0x0);
994 + __phy_write(phydev, 0x10, 0x8f80);
995 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
996 +
997 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
998 + __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
999 + FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
1000 +
1001 + __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
1002 + FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
1003 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1004 +
1005 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1006 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1007 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1008 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
1009 +}
1010 +
1011 +static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1012 + u8 start_pair, u8 end_pair)
1013 +{
1014 + u8 pair_n;
1015 + int ret;
1016 +
1017 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1018 + /* TX_OFFSET & TX_AMP have no SW calibration. */
1019 + switch (cal_item) {
1020 + case TX_VCM:
1021 + ret = tx_vcm_cal_sw(phydev, pair_n);
1022 + break;
1023 + default:
1024 + return -EINVAL;
1025 + }
1026 + if (ret)
1027 + return ret;
1028 + }
1029 + return 0;
1030 +}
1031 +
1032 +static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1033 + u8 start_pair, u8 end_pair, u32 *buf)
1034 +{
1035 + u8 pair_n;
1036 + int ret;
1037 +
1038 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1039 + /* TX_VCM has no efuse calibration. */
1040 + switch (cal_item) {
1041 + case REXT:
1042 + ret = rext_cal_efuse(phydev, buf);
1043 + break;
1044 + case TX_OFFSET:
1045 + ret = tx_offset_cal_efuse(phydev, buf);
1046 + break;
1047 + case TX_AMP:
1048 + ret = tx_amp_cal_efuse(phydev, buf);
1049 + break;
1050 + case TX_R50:
1051 + ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1052 + break;
1053 + default:
1054 + return -EINVAL;
1055 + }
1056 + if (ret)
1057 + return ret;
1058 + }
1059 +
1060 + return 0;
1061 +}
1062 +
1063 +static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1064 + enum CAL_MODE cal_mode, u8 start_pair,
1065 + u8 end_pair, u32 *buf)
1066 +{
1067 + int ret;
1068 +
1069 + switch (cal_mode) {
1070 + case EFUSE_M:
1071 + ret = cal_efuse(phydev, cal_item, start_pair,
1072 + end_pair, buf);
1073 + break;
1074 + case SW_M:
1075 + ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1076 + break;
1077 + default:
1078 + return -EINVAL;
1079 + }
1080 +
1081 + if (ret) {
1082 + phydev_err(phydev, "cal %d failed\n", cal_item);
1083 + return -EIO;
1084 + }
1085 +
1086 + return 0;
1087 +}
1088 +
1089 +static int mt798x_phy_calibration(struct phy_device *phydev)
1090 +{
1091 + int ret = 0;
1092 + u32 *buf;
1093 + size_t len;
1094 + struct nvmem_cell *cell;
1095 +
1096 + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1097 + if (IS_ERR(cell)) {
1098 + if (PTR_ERR(cell) == -EPROBE_DEFER)
1099 + return PTR_ERR(cell);
1100 + return 0;
1101 + }
1102 +
1103 + buf = (u32 *)nvmem_cell_read(cell, &len);
1104 + if (IS_ERR(buf))
1105 + return PTR_ERR(buf);
1106 + nvmem_cell_put(cell);
1107 +
1108 + if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
1109 + phydev_err(phydev, "invalid efuse data\n");
1110 + ret = -EINVAL;
1111 + goto out;
1112 + }
1113 +
1114 + ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1115 + if (ret)
1116 + goto out;
1117 + ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1118 + if (ret)
1119 + goto out;
1120 + ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1121 + if (ret)
1122 + goto out;
1123 + ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1124 + if (ret)
1125 + goto out;
1126 + ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1127 + if (ret)
1128 + goto out;
1129 +
1130 +out:
1131 + kfree(buf);
1132 + return ret;
1133 +}
1134 +
1135 +static int mt798x_phy_config_init(struct phy_device *phydev)
1136 +{
1137 + switch (phydev->drv->phy_id) {
1138 + case MTK_GPHY_ID_MT7981:
1139 + mt7981_phy_finetune(phydev);
1140 + break;
1141 + case MTK_GPHY_ID_MT7988:
1142 + mt7988_phy_finetune(phydev);
1143 + break;
1144 + }
1145 +
1146 + mt798x_phy_common_finetune(phydev);
1147 + mt798x_phy_eee(phydev);
1148 +
1149 + return mt798x_phy_calibration(phydev);
1150 +}
1151 +
1152 +static struct phy_driver mtk_socphy_driver[] = {
1153 + {
1154 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
1155 + .name = "MediaTek MT7981 PHY",
1156 + .config_init = mt798x_phy_config_init,
1157 + .config_intr = genphy_no_config_intr,
1158 + .handle_interrupt = genphy_handle_interrupt_no_ack,
1159 + .probe = mt798x_phy_calibration,
1160 + .suspend = genphy_suspend,
1161 + .resume = genphy_resume,
1162 + .read_page = mtk_socphy_read_page,
1163 + .write_page = mtk_socphy_write_page,
1164 + },
1165 + {
1166 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
1167 + .name = "MediaTek MT7988 PHY",
1168 + .config_init = mt798x_phy_config_init,
1169 + .config_intr = genphy_no_config_intr,
1170 + .handle_interrupt = genphy_handle_interrupt_no_ack,
1171 + .probe = mt798x_phy_calibration,
1172 + .suspend = genphy_suspend,
1173 + .resume = genphy_resume,
1174 + .read_page = mtk_socphy_read_page,
1175 + .write_page = mtk_socphy_write_page,
1176 + },
1177 +};
1178 +
1179 +module_phy_driver(mtk_socphy_driver);
1180 +
1181 +static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
1182 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
1183 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
1184 + { }
1185 +};
1186 +
1187 +MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1188 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1189 +MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1190 +MODULE_LICENSE("GPL");
1191 +
1192 +MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
1193 --- a/drivers/net/phy/mediatek-ge.c
1194 +++ b/drivers/net/phy/mediatek-ge.c
1195 @@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
1196 module_phy_driver(mtk_gephy_driver);
1197
1198 static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
1199 - { PHY_ID_MATCH_VENDOR(0x03a29400) },
1200 + { PHY_ID_MATCH_EXACT(0x03a29441) },
1201 + { PHY_ID_MATCH_EXACT(0x03a29412) },
1202 { }
1203 };
1204
John Crispins staging tree